Abstract: A high voltage thin film transistor comprising a substrate upon which is supported a non-single crystal semiconductor active layer, spaced from a pair of conductive gate electrodes by a gate dielectric layer, wherein one of the gate electrodes in the device control electrode and the other is a dummy-drain electrode. Heavily doped semiconductor source and drain electrodes are in substantial alignment with the outer edges of the gate electrodes, the source electrode being aligned with the device control electrode and the drain electrode being aligned with the dummy-drain electrode. The active layer has intrinsic or virtually intrinsic regions thereof in opposition to the bodies of each of the gate electrodes, and an offset region, between the gate electrodes, having a lower depant level than the source and drain electrodes, which is aligned with the inner edges of the gate electrodes.

Abstract: A high voltage thin film transistor comprising a substrate upon which is supported a non-single crystal semiconductor active layer, spaced from a pair of conductive gate electrodes by a gate dielectric layer, wherein one of the gate electrodes is the device control electrode and the other is a dummy-drain electrode. Heavily doped semiconductor source and drain electrodes are in substantially alignment with the outer edges of the gate electrodes, the source electrode being aligned with the device control electrode and the drain electrode being aligned with the dummy-drain electrode. The active layer has intrinsic or virtually intrinsic region thereof in opposition to the bodies of each of the gate electrodes, and an offset region, between the gate electrodes, having a lower dopant level than the source and drain electrodes, which is aligned with the inner edges of the gate electrodes.

Abstract: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped junction is aligned with the outboard alignment members.

Abstract: A method of forming large grain polycrystalline films by deep ion implantation into a composite structure, comprising a layer of amorphous semiconductor material upon an insulating substrate. Implantation is of a given ion species at an implant energy and dosage sufficient to distrupt the interface between the amorphous layer and the substrate and to retard the process of nucleation in subsequent random crystallization upon thermal annealing.