Patents by Inventor Tien-Hao Tang

Tien-Hao Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9142545
    Abstract: The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: September 22, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Chun Chen, Li-Cih Wang, Lu-An Chen, Tien-Hao Tang
  • Patent number: 9142540
    Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain and a source formed in the substrate at respective two sides of the gate, and a doped region formed in the source. The drain and the source comprise a first conductivity type and the doped region comprises a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 22, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ning He, Lu-An Chen, Tien-Hao Tang
  • Publication number: 20150243776
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) is provided. A substrate has a deep well with a second conductive type therein. A gate is disposed on the substrate. A first doped region of a second conductive type and a second doped region of a first conductive type are located in the deep well and at the corresponding two sides of the gate. A drain region of a second conductive type is located in the first doped region. A drain contact is disposed on the drain region. A doped region of a first conductive type is located in the first doped region and under the drain region but not directly below the drain contact. A source region is located in the second doped region. A field drift metal oxide semiconductor (FDMOS) which is similar to the laterally diffused metal oxide semiconductor (LDMOS) is also provided.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Lu-An Chen, Tien-Hao Tang
  • Publication number: 20150236010
    Abstract: The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.
    Type: Application
    Filed: February 17, 2014
    Publication date: August 20, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Chun Chen, Li-Cih Wang, Lu-An Chen, Tien-Hao Tang
  • Publication number: 20150228771
    Abstract: An electrostatic discharge protection structure includes a first well, a second well disposed in the first well, a first and a second doped region disposed in the first well, a third and a fourth doped region disposed in the second well, a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the fourth doped region.
    Type: Application
    Filed: February 11, 2014
    Publication date: August 13, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Lu-An Chen, Ya-Ting Lin, Tien-Hao Tang
  • Publication number: 20150221634
    Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.
    Type: Application
    Filed: April 13, 2015
    Publication date: August 6, 2015
    Inventors: Lu-An Chen, Tien-Hao Tang
  • Publication number: 20150221632
    Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 9093565
    Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: July 28, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 9041110
    Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: May 26, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lu-An Chen, Tien-Hao Tang
  • Publication number: 20150137255
    Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Yung-Ju Wen, Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20150129977
    Abstract: A semiconductor electrostatic discharge (ESD) protection apparatus comprises at least one elementary transistor with a first conductivity type, a well region with a second conductivity type, a guard ring with the second conductivity type and a semiconductor interval region. The elementary transistor is formed in the well region. The guard ring surrounds the at least one elementary transistor. The semiconductor interval region is disposed between the elementary transistor and the guard ring in order to surrounds the elementary transistor, wherein the semiconductor interval region is an undoped region, a doped region with the first conductivity type or a doped region with the second conductivity type that has a doping concentration substantially less than that of the well region.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yu-Chun CHEN, Chang-Tzu Wang, Tien-Hao Tang
  • Publication number: 20150123184
    Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 8981488
    Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes a first field-effect transistor (FET), a second FET, an isolation structure, and a body electrode. The first FET includes a first active body having a first type conductivity. The second FET includes a second active body having the first type conductivity. The first active body and the second active body are isolated from each other by the isolation structure. The body electrode has the first type conductivity and formed in the second active body.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: March 17, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Yung-Ju Wen, Tien-Hao Tang, Chang-Tzu Wang
  • Patent number: 8981521
    Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 17, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Tzu Wang, Pei-Shan Tseng, Tien-Hao Tang
  • Publication number: 20150054132
    Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Chang-Tzu Wang, Pei-Shan Tseng, Tien-Hao Tang
  • Patent number: 8963202
    Abstract: A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corporation
    Inventors: Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20150014809
    Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20150008529
    Abstract: Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.
    Type: Application
    Filed: July 8, 2013
    Publication date: January 8, 2015
    Inventors: Yung-Ju Wen, Chang-Tzu Wang, Tien-Hao Tang
  • Patent number: 8896024
    Abstract: Provided is an electrostatic discharge (ESD) protection structure including a first and a second well region adjacent to each other, a first and a second doped region disposed in the first well region, a fourth and a fifth doped region disposed in the second well region, and a third doped region disposed in the first region and extending into the second well region. The second doped region is disposed between the first and the third doped regions, forming a diode with the first doped region, forming, together with the first well region and the second well region, a first bipolar junction transistor (BJT) electrically connecting to the diode, and having no contact window disposed thereon. The fourth doped region is disposed between the third and the fifth doped regions, forming a second BJT with the second well region and the first well region.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Chun Chen, Li-Cih Wang, Lu-An Chen, Tien-Hao Tang
  • Patent number: 8890250
    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 18, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang