Abstract: An electrostatic discharge protection device comprises a substrate with a first conductivity, a gate, a drain structure and a source structure. The gate is disposed on a surface of the substrate. The drain structure with a second conductivity type comprises a first doping region with a first doping concentration disposed adjacent to the gate and extending into the substrate from the surface of the substrate, a second doping region extending into and stooped at the first doping region from the surface of the substrate and having a second doping concentration substantially greater than the first doping concentration, and a third doping region disposed in the substrate beneath the second doping region and having a third doping concentration substantially greater than the first doping concentration. The source structure with the second conductivity is disposed in the substrate and adjacent to the gate electrode.

Abstract: Provided is a metal oxide semiconductor device, including a substrate, a gate, a first-type first heavily doped region, a first-type drift region, a second-type first heavily doped region, a contact, a first electrode, and a second electrode. The gate is disposed on the substrate. The first-type first heavily doped region is disposed in the substrate at a side of the gate. The first-type drift region is disposed in the substrate at another side of the gate. The second-type first heavily doped region is disposed in the first-type drift region. The contact is electrically connected to the second-type first heavily doped region. The contact is the closest contact to the gate on the first-type drift region. The first electrode is electrically connected to the contact, and the second electrode is electrically connected to the first-type first heavily doped region and the gate.

Abstract: An electrostatic discharge protection circuit is located between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first semiconductor switch and a second semiconductor switch. The first semiconductor switch is electrically connected to the first voltage terminal. If a voltage at the first voltage terminal complies with a starting condition, the first semiconductor switch is turned on, so that an electrostatic discharge current flows through the first voltage terminal and the first semiconductor switch. The second semiconductor switch is electrically connected between the first semiconductor switch and the second voltage terminal, wherein the electrostatic discharge current from the first semiconductor switch passes to the second voltage terminal through the second semiconductor switch.

Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

Abstract: An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs.

Abstract: An electrostatic protection circuit includes a strained transistor array, an unstrained transistor, and a control circuit. The strained transistor array has a first end electrically connected to a bias terminal. The unstrained transistor has a first end electrically connected to the bias terminal. The control circuit is electrically connected to a second end of the strained transistor array, a second end of the unstrained transistor and a ground terminal. The control circuit controls impedance between the second end of the strained transistor array and the ground terminal according to current flowing through the unstrained transistor. The electrostatic protection circuit is capable of preventing latch-up effect.

Abstract: A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source.

Abstract: An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

Abstract: An electrostatic discharge protection device comprises a substrate with a first conductivity, a gate, a drain structure and a source structure. The gate is disposed on a surface of the substrate. The drain structure with a second conductivity type comprises a first doping region with a first doping concentration disposed adjacent to the gate and extending into the substrate from the surface of the substrate, a second doping region extending into and stooped at the first doping region from the surface of the substrate and having a second doping concentration substantially greater than the first doping concentration, and a third doping region disposed in the substrate beneath the second doping region and having a third doping concentration substantially greater than the first doping concentration. The source structure with the second conductivity is disposed in the substrate and adjacent to the gate electrode.

Abstract: An electrostatic discharge protection circuit is located between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first semiconductor switch and a second semiconductor switch. The first semiconductor switch is electrically connected to the first voltage terminal. If a voltage at the first voltage terminal complies with a starting condition, the first semiconductor switch is turned on, so that an electrostatic discharge current flows through the first voltage terminal and the first semiconductor switch. The second semiconductor switch is electrically connected between the first semiconductor switch and the second voltage terminal, wherein the electrostatic discharge current from the first semiconductor switch passes to the second voltage terminal through the second semiconductor switch.

Abstract: An ESD clamping device comprises a plurality of fingers each comprising a source region of first conductivity type formed in a substrate of second conductivity type, a drain region of said first conductivity type formed in the substrate, and a gate formed over the substrate and between the source and drain regions. At least one of the fingers each has an ESD implantation region formed in the substrate and partially underlying the drain region of the finger, the ESD implantation region being a heavily doped region of said second conductivity type. Furthermore, at least one of the fingers has a gate extension portion projecting from the gate and demarcating an additional region in at least the drain region of the finger, the additional region of said second conductivity type being electrically connected to at least one of the gate and the substrate of each of the fingers.

Abstract: An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.

Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

Abstract: An ESD clamping device comprises a plurality of fingers each comprising a source region of first conductivity type formed in a substrate of second conductivity type, a drain region of said first conductivity type formed in the substrate, and a gate formed over the substrate and between the source and drain regions. At least one of the fingers each has an ESD implantation region formed in the substrate and partially underlying the drain region of the finger, the ESD implantation region being a heavily doped region of said second conductivity type. Furthermore, at least one of the fingers has a gate extension portion projecting from the gate and demarcating an additional region in at least the drain region of the finger, the additional region of said second conductivity type being electrically connected to at least one of the gate and the substrate of each of the fingers.

Abstract: An SCR device includes a substrate, a plurality of isolation structures defining a first region and a second region in the substrate, an n well disposed in the substrate, an n type first doped region disposed in the first region in the substrate, a p type second doped region disposed in the second region in the substrate, and a p type third doped region (PESD implant region) disposed underneath the first doped region in the first region in the substrate. The well is disposed underneath the first region and the second region, and the third doped region isolates the first doped region from the well.

Abstract: A LDMOS device for an ESD protection circuit is provided. The LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, a body region of the first conductivity type, first and second doped regions of the second conductivity type, and a gate electrode. The deep well region is disposed in the substrate. The body region and the first doped region are respectively disposed in the deep well region. The second doped region is disposed in the body region. The gate electrode is disposed on the deep well region between the first and second doped regions. It is noted that the body region does not include a doped region of the first conductivity type having a different doped concentration from the body region.

Abstract: An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.

Abstract: An ESD protection device including a substrate, a gate structure, a source region, a drain region and a first implanted region is provided. The gate structure includes a gate dielectric layer and a gate sequentially disposed on the substrate. The source region and the drain region are disposed in the substrate beside the gate structure. The first implanted region has the same conductivity type as the drain region. The first implanted region is disposed below the drain region, and the border thereof does not exceed the border of the drain region.

Abstract: A LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, two body regions of the first conductivity type, a body connection region of the first conductivity type, two source regions of the second conductivity type, a drain region of the second conductivity type, a channel region, and a gate electrode. The body regions are disposed in the deep well region configured in the substrate. The body connection region is disposed in the deep well region to connect the body regions. Each of the source regions is disposed in the body region. The drain region is disposed in the deep well between the source regions. The channel region is disposed in a portion of the body region. The gate electrode is disposed on the deep well region between the source regions and the drain region and covers the channel region.

Abstract: A LDMOS device for an ESD protection circuit is provided. The LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, a body region of the first conductivity type, first and second doped regions of the second conductivity type, and a gate electrode. The deep well region is disposed in the substrate. The body region and the first doped region are respectively disposed in the deep well region. The second doped region is disposed in the body region. The gate electrode is disposed on the deep well region between the first and second doped regions. It is noted that the body region does not include a doped region of the first conductivity type having a different doped concentration from the body region.