Patents by Inventor Tien-Lu Lin
Tien-Lu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10490500Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.Type: GrantFiled: February 24, 2017Date of Patent: November 26, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Lun Kao, Hsiang-Wei Liu, Tai-I Yang, Jian-Hua Chen, Yu-Chieh Liao, Yung-Chih Wang, Tien-Lu Lin
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Patent number: 10468349Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.Type: GrantFiled: October 19, 2018Date of Patent: November 5, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
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Publication number: 20190252319Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate and laterally separated in a first direction from a first closest air-gap by a first distance. A second metal wire is arranged within the ILD layer and is laterally separated in the first direction from a second closest air-gap by a second distance that is larger than the first distance. A via is disposed on an upper surface of the second metal wire.Type: ApplicationFiled: April 25, 2019Publication date: August 15, 2019Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
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Publication number: 20190244897Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure over a substrate, and a first interconnect structure arranged within the dielectric structure. A lower interconnect structure is arranged within the dielectric structure. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials. The first interconnect structure continuously extends from directly over a topmost surface of the lower interconnect structure facing away from the substrate to along opposing outer sidewalls of the lower interconnect structure.Type: ApplicationFiled: April 15, 2019Publication date: August 8, 2019Inventors: Hsiang-Wei Liu, Tai-I Yang, Cheng-Chi Chuang, Tien-Lu Lin
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Publication number: 20190157423Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: ApplicationFiled: January 7, 2019Publication date: May 23, 2019Inventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Patent number: 10290580Abstract: The present disclosure, in some embodiments, relates to an integrated chip having a back-end-of-the-line interconnect stack. The integrated chip has a dielectric structure arranged over a substrate. A first interconnect structure is arranged within the dielectric structure and has sidewalls and a horizontally extending surface that define a recess within a lower surface of the first interconnect structure facing the substrate. A lower interconnect structure is arranged within the dielectric structure and extends from within the recess to a location between the first interconnect structure and the substrate. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials.Type: GrantFiled: November 21, 2017Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiang-Wei Liu, Tai-I Yang, Cheng-Chi Chuang, Tien-Lu Lin
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Patent number: 10276498Abstract: In some embodiments, the present disclosure relates to an interconnect structure. The interconnect structure has a first dielectric layer disposed over a substrate and a conductive structure arranged within the first dielectric layer. An air-gap separates sidewalls of the conductive structure from the first dielectric layer. The air-gap continuously extends from a first side of the conductive structure to an opposing second side of the conductive structure.Type: GrantFiled: December 22, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
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Publication number: 20190058033Abstract: A semiconductor device includes a substrate, a liner, and an isolation structure. The substrate has at least one first semiconductor fin and at least one second semiconductor fin. The liner is disposed on at least one sidewall of the second semiconductor fin. The isolation structure is disposed over the substrate, in which the isolation structure is in contact with the first semiconductor fin and the liner.Type: ApplicationFiled: August 15, 2017Publication date: February 21, 2019Inventors: Tien-Lu LIN, Jung-Hung CHANG
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Publication number: 20190051595Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.Type: ApplicationFiled: October 19, 2018Publication date: February 14, 2019Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
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Publication number: 20190019753Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphehe layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.Type: ApplicationFiled: September 7, 2018Publication date: January 17, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-I YANG, Tien-I BAO, Tien-Lu LIN, Wei-Chen CHU
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Patent number: 10177242Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: GrantFiled: July 3, 2017Date of Patent: January 8, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Patent number: 10109519Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A conductive feature over a substrate is provided. A first dielectric layer is deposited over the conductive feature and the substrate. A via-forming-trench (VFT) is formed in the first dielectric layer to expose the conductive feature and the substrate around the conductive feature. The VFT is filled in by a sacrificial layer. A via-opening is formed in the sacrificial layer to expose the conductive feature. A metal plug is formed in the via-opening to connect to the conductive feature. The sacrificial layer is removed to form a surrounding-vacancy around metal plug and the conductive feature. A second dielectric layer is deposited over the substrate to seal a portion of the surrounding-vacancy to form an enclosure-air-gap all around the metal plug and the conductive feature.Type: GrantFiled: September 27, 2016Date of Patent: October 23, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiang-Lun Kao, Tien-Lu Lin, Yung-Chih Wang, Cheng-Chi Chuang
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Patent number: 10109582Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.Type: GrantFiled: March 10, 2017Date of Patent: October 23, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
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Publication number: 20180301409Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.Type: ApplicationFiled: June 12, 2018Publication date: October 18, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I YANG, Yu-Chieh LIAO, Tien-Lu LIN, Tien-I BAO
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Patent number: 10103102Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer over a semiconductor substrate. The semiconductor device structure also includes a first conductive feature in the dielectric layer. A portion of the dielectric layer has a top surface that is provided on a different level in relation to a top surface of the first conductive feature. The semiconductor device structure further includes a second conductive feature in the dielectric layer and extending from a bottom surface of the first conductive feature. The portion of the dielectric layer is separated from the second conductive feature by a gap. A distance between the portion of the dielectric layer and the second conductive feature becomes smaller along a direction from the top surface of the first conductive feature towards the bottom surface of the first conductive feature.Type: GrantFiled: December 27, 2017Date of Patent: October 16, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hua Chen, Tai-I Yang, Cheng-Chi Chuang, Chia-Tien Wu, Tien-Lu Lin, Tien-I Bao
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Patent number: 10074607Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect structure formed over the substrate. The interconnect structure includes a first dielectric layer formed over the substrate, and a first graphene layer formed in and on the first dielectric layer. The first graphene layer includes a first portion in the first dielectric layer and a second portion on the first dielectric layer and a first insulating layer formed over the first portion of the first graphene layer.Type: GrantFiled: February 5, 2016Date of Patent: September 11, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-I Yang, Tien-I Bao, Tien-Lu Lin, Wei-Chen Chu
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Patent number: 10032713Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first conductive plug and a second conductive plug over the semiconductor substrate and adjacent to each other. The semiconductor device structure includes a first conductive via structure and a second conductive via structure over the semiconductor substrate and adjacent to each other. A first distance between the first conductive plug and the second conductive plug is less than a second distance between the first conductive via structure and the second conductive via structure. A first height of the first conductive plug is greater than a second height of the first conductive via structure.Type: GrantFiled: January 27, 2016Date of Patent: July 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Chih Wang, Carlos H. Diaz, Tien-Lu Lin
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Patent number: 10002826Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.Type: GrantFiled: October 27, 2014Date of Patent: June 19, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Tai-I Yang, Yu-Chieh Liao, Tien-Lu Lin, Tien-I Bao
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Publication number: 20180138124Abstract: In some embodiments, the present disclosure relates to an interconnect structure. The interconnect structure has a first dielectric layer disposed over a substrate and a conductive structure arranged within the first dielectric layer. An air-gap separates sidewalls of the conductive structure from the first dielectric layer. The air-gap continuously extends from a first side of the conductive structure to an opposing second side of the conductive structure.Type: ApplicationFiled: December 22, 2017Publication date: May 17, 2018Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
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Publication number: 20180122739Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer over a semiconductor substrate. The semiconductor device structure also includes a first conductive feature in the dielectric layer. A portion of the dielectric layer has a top surface that is provided on a different level in relation to a top surface of the first conductive feature. The semiconductor device structure further includes a second conductive feature in the dielectric layer and extending from a bottom surface of the first conductive feature. The portion of the dielectric layer is separated from the second conductive feature by a gap. A distance between the portion of the dielectric layer and the second conductive feature becomes smaller along a direction from the top surface of the first conductive feature towards the bottom surface of the first conductive feature.Type: ApplicationFiled: December 27, 2017Publication date: May 3, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hua CHEN, Tai-I YANG, Cheng-Chi CHUANG, Chia-Tien WU, Tien-Lu LIN, Tien-I BAO