Abstract: DRAM cell arrangement with vertical MOS transistors, and method for its fabrication. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.

Abstract: The upper capacitor electrode (10) of the trench capacitor is connected to an epitaxially grown source/drain region (21) of the select transistor (20) by a tubular, monocrystalline Si contact-making region (7.1). The gate electrode layer (24) has an oval peripheral contour around the transistor (20), the oval peripheral contours of the gate electrode layers (24) of memory cells arranged in a row along a word line forming overlap regions (24.3) in order to increase the packing density.

Abstract: As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.

Abstract: A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.

Abstract: A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.

Abstract: An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive effect with a transistor control and cost-effective memory cells with a magnetoresistive effect with memory elements connected between the word lines and bit lines. The memory elements connected directly between the bit line and the word line are preferably inserted in memory cell arrays that can be stacked one above the other above the memory cells with the transistor, and thereby achieve a high integration density. The fact that the memory, which contains both types and thereby satisfies all the system requirements, is fabricated in one module and in one process sequence considerably lowers the fabrication costs.

Abstract: A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire being a semiconducting and/or metallically conductive nanowire. The field-effect transistor also has at least one nanotube, which forms a gate region of the field-effect transistor, the nanotube being a semiconducting and/or metallically conductive nanotube. The nanowire and the nanotube are arranged at a distance from one another or set up in such a manner that it is substantially impossible for there to be a tunneling current between the nanowire and the nanotube, and that the conductivity of the channel region of the nanowire can be controlled by means of a field effect as a result of an electric voltage being applied to the nanotube.

Abstract: In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.

Abstract: A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

Abstract: The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor substrate. The field effect transistor has a source area, a drain area, a channel area and a gate stack. The gate stack has at least one ferroelectric layer and at least one thin diffusion barrier layer being arranged between the lowest ferroelectric layer and the semiconductor substrate and being configured in such a way that an out-diffusion of the components of the ferroelectric layer into the semiconductor substrate is essentially prevented.

Abstract: In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.

Abstract: In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.

Abstract: To simplify a method for manufacturing a memory device having a multiplicity of MRAM cells in a crossing area of conductor elements, a method for manufacturing a semiconductor circuit system, in particular, a memory device or the like, having a plurality of memory cells includes the step of structuring each of the memory elements simultaneously with the structuring of the first and second conductor elements.

Abstract: An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive effect with a transistor control and cost-effective memory cells with a magnetoresistive effect with memory elements connected between the word lines and bit lines. The memory elements connected directly between the bit line and the word line are preferably inserted in memory cell arrays that can be stacked one above the other above the memory cells with the transistor, and thereby achieve a high integration density. The fact that the memory, which contains both types and thereby satisfies all the system requirements, is fabricated in one module and in one process sequence considerably lowers the fabrication costs.

Abstract: A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

Abstract: The method of the invention, in contrast to conventional trench capacitors wherein the memory node is formed in a trench, normally in the form of a drilled hole, includes the steps of forming the memory node in the monocrystalline silicon of the substrate and remains as a web during an etching process while a trench is filled with the common opposing electrode of the memory cell array. In the method, it is advantageous for the selection transistor to be in the form of a vertical transistor above the memory node in the freestanding web.

Abstract: A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-section of the lower area, parallel to the main surface, matches the cross-section of the upper area, particularly in the vicinity the upper area, with the following difference: each corner is rounded, whereby the cross section of the lower area is smaller than the cross-section of the upper area. In order to produce the indentation, the upper area is provided with an auxiliary spacer that is rounded by isotropic etching. The lower area is produced by selectively etching the substrate to form an auxiliary spacer.

Abstract: An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.

Abstract: The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown epitaxial layer. The selective epitaxial layer is so structured that a ridge is formed from it. Next, the ridge is partially undercut, whereby the etch selectivity of the ridge relative to the first insulating layer is utilized for a wet-chemical etching procedure. Next, a contact layer is arranged in the undercut region, which connects the ridge and a transistor that has been formed in the ridge to the conductive trench fill. Lateral margin ridges are then formed next to the ridge as a gate, and a doped region is incorporated into the ridge as a source/drain zone of the transistor.

Abstract: A DRAM memory cell includes a MOSFET selection transistor having a drain region and a source region in a semiconductor substrate column. A current channel, which is capable of being actuated by a control gate electrode extends in a vertical direction between the drain and source regions. A capacitor is stacked under the selection transistor and electrically connected to the source region in the semiconductor substrate column. Above the selection transistor is a metal bit line electrically connected to the drain region in the semiconductor substrate column. A metal word line in direct electrical communication with the control gate electrode of the selection transistor extends perpendicularly with respect to the metal bit line.