Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.

Abstract: A method is provided to retrieve a display resolution used by a computing device in an online conference. With the display resolution, a boundary associated with the display resolution is displayed. The boundary is configured to define a display area shown on the computing device.

Abstract: A system for designing a circuit, which includes a module, uses a computer. A user may program or adapt the computer to perform computer-aided design functions. The computer obtains a description of the module from the user. The computer parses the description of the module to identify a port of the module, and to obtain information about the port. The computer presents to the user the information that it has obtained about the port.

Abstract: Network conference application software measures communication latency between itself and an endpoint in a conference. Endpoints with excessive latency are identified as having a delay. Information about endpoints with delays is displayed by the network conference application during a network conference. The displayed information may include the ratio of endpoints with delays to total endpoints, and a representation of data previously transmitted by the conference application that an endpoint with a delay is currently viewing. A graphical user interface may be used for displaying information about endpoints with delays.

Abstract: The present invention provides a method and apparatus for a trusted service provider (TSP) which assists with the secure exchange of data across the public switched telephone network. Communications are routed via a TSP, which uses cryptographic techniques to conceal the identities (e.g., telephone numbers) of the call initiator and call recipient, thereby preventing traffic analysis attacks. The TSP also performs cryptographic handshakes with the call initiator and call recipient to authenticate callers. The TSP further provides cryptographic keying material which communicants may use to help protect communications and to directly authenticate and identify each other. Although the TSP is trusted to negotiate the connection and is involved in the process, the communicants can perform their own key agreement and authentication for protecting data routed via the TSP.

Abstract: The present invention provides a method and apparatus for a trusted service provider (TSP) which assists with the secure exchange of data across the public switched telephone network. Communications are routed via a TSP, which uses cryptographic techniques to conceal the identities (e.g., telephone numbers) of the call initiator and call recipient, thereby preventing traffic analysis attacks. The TSP also performs cryptographic handshakes with the call initiator and call recipient to authenticate callers. The TSP further provides cryptographic keying material which communicants may use to help protect communications and to directly authenticate and identify each other. Although the TSP is trusted to negotiate the connection and is involved in the process, the communicants can perform their own key agreement and authentication for protecting data routed via the TSP.

Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.

Abstract: Embodiments relate to systems and methods for generating an electronic upsell directory A main networked store can communicate with a set of affiliate sites, each of which offers distinct products or services from individualized affiliate catalogs. The affiliate catalogs are each based on a core catalog available from the main store. When a user initiates a purchase transaction at an affiliate site, a transaction profile is transmitted to the main store. The main store examines the transaction profile to match purchased items against an upsell table containing the catalogs of not just the affiliate site conducting the transaction, but the entire set of affiliate sites. Products or services that form suitable options to the user's selected purchase can be aggregated across the affiliate sites and associated catalogs, and presented in an upsell dialog to the user. The user can thereby select upgrades or options from a broader array of sources.

Abstract: A programmable logic device (PLD) is provided. The PLD includes a microprocessing unit (MPU) and a memory region functioning in a read only state. A Joint Test Action Group (JTAG) debug module in communication with the memory region is included in the PLD. The JTAG debug module is able to detect a breakpoint causing an interruption of a processing sequence executed by the MPU. Write control circuitry capable of issuing a signal enabling the memory region to transition from the read only state disallowing writes to a second state accepting write data from the MPU is included in the JTAG debug circuitry. In one embodiment, the write control circuitry issues the signal in response to a breakpoint induced either through hardware or software. A method of debugging a PLD is also provided.

Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

Abstract: Methods and apparatus are provided for efficiently implementing a programmable chip using hardware description source files passed through multiple tools. A hardware description language source file is provided with mechanisms to allow tool-specific code to be handled by both a synthesis tool and by a simulation tool. Instructions are provided to direct a synthesis tool to read as code comments that a simulation tool is configured to disregard.

Abstract: A tension control assembly including a rotating member, a braking member, at least one brake pad, a means for driving the at least one brake pad against the braking member, and a temperature sensing means. The braking member is attached to the rotating member. The at least one brake pad is positioned adjacent to the braking member. The means for driving the at least one brake pad against the braking member forces frictional contact between the at least one brake pad and the braking member, thus providing torque to the rotating member. The temperature sensing means measures the temperature of the at least one brake pad.

Abstract: A system for designing a circuit, which includes a module, uses a computer. A user may program or adapt the computer to perform computer-aided design functions. The computer obtains a description of the module from the user. The computer parses the description of the module to identify a port of the module, and to obtain information about the port. The computer presents to the user the information that it has obtained about the port.

Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.

Abstract: Methods and apparatus are provided for configuring and generating a sequence of discrete output signal values. A microcontroller writes output signal values to memory and provides address and timing information to a streaming output peripheral. The streaming output peripheral uses the address and timing information to read output signals values from memory and provide the output signal values in a clock cycle accurate manner.

Abstract: A system and method is disclosed for controlling the input electrical current to an infusion pump stepper motor based on predetermined torque requirements. The system can include a motor controller and a non-volatile memory containing expected load torque values throughout a pump cycle. Responsive to the expected load torque values, the motor controller provides the stepper motor with a varying electrical current for overcoming load torque at each point in the pumping cycle. Additional factors can also be considered for varying the electrical current. These factors include, but are not limited to, temperature, pressure, and elapsed operating time.

Abstract: A system for designing a circuit, which includes a module, uses a computer. A user may program or adapt the computer to perform computer-aided design functions. The computer obtains a description of the module from the user. The computer parses the description of the module to identify a port of the module, and to obtain information about the port. The computer presents to the user the information that it has obtained about the port.

Abstract: Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on an integrated circuit. A slave side arbitrator corresponding to a single slave component and coupled to multiple master components can be used to provide a master component access to a slave component.

Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.

Abstract: Methods and apparatus are provided for efficiently implementing a programmable chip using hardware description source files passed through multiple tools. A hardware description language source file is provided with mechanisms to allow tool-specific code to be handled by both a synthesis tool and by a simulation tool. Instructions are provided to direct a synthesis tool to read as code comments that a simulation tool is configured to disregard.