Abstract: Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.

Abstract: A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL.

Abstract: Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.

Abstract: Techniques are provided for dynamically reconfiguring programmable circuit blocks on integrated circuits during user mode. First configuration bits are loaded from first configuration scan registers into second configuration scan registers during configuration mode. The first configuration bits are used to configure programmable settings of a programmable circuit block. During user mode, second configuration bits are transmitted from a pin to the second configuration scan registers without transferring the second configuration bits through the first configuration scan registers. The second configuration bits are used to reconfigure the programmable settings of the programmable circuit block during the user mode. Also, phase shift circuitry can dynamically shift the phase of an output clock signal by selecting a different input clock signal. The phase shift circuitry has a delay circuit that allows the phase of a high frequency clock signal to be shifted without causing glitches in the clock signal.

Abstract: An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.

Abstract: Techniques are provided for dynamically adjusting the frequency range of phase-locked loops (PLLs). Phase detection circuitry in a PLL generates a control signal in response to a periodic input signal and a feedback signal. When the control signal deviates outside a valid range, the input frequency range of the PLL is dynamically adjusted to include the periodic input signal frequency. The input frequency range of the PLL is adjusted by changing one or more frequency ratios in the PLL. The resistance and/or capacitance of a loop filter in the PLL can be dynamically adjusted to control the bandwidth of the PLL.

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract: High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.

Abstract: Methods and apparatus are provided for varying the bandwidth of a loop filter in a loop circuit (e.g., a phase-locked loop circuit). The loop filter can include first and second resistor circuitries coupled to a capacitor. One of the resistor circuitries can be coupled to an output of the loop circuit in response to selection of a mode of operation. The resistor circuitries can each include a plurality of resistors that can be selectively coupled in series to the capacitor or bypassed. In addition, the output of the loop circuit can be coupled to a second capacitor. Either or both of the capacitors can be programmable.

Abstract: A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

Abstract: Voltage controlled oscillator (VCO) circuitry with low phase noise and a wide range of operating frequencies is presented. The VCO circuitry includes circuitry with two or more VCO sub-circuits, each sub-circuit being optimized to produce output clock signals with low phase noise and with frequencies in a different range. Sub-circuits with gear inputs may be operative to produce output clock signals in a lower range of frequencies, while sub-circuits optimized for high speed operation may be used to produce output signals in a higher range of frequencies. A control circuit may be used to produce a control signal coupled to all sub-circuits. The control signal may set the operating frequency of the sub-circuits.

Abstract: A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.

Abstract: The architecture of a programmable logic device (“PLD”) is modified in one or more of several respects to facilitate inclusion of high-speed serial interface (“HSSI”) circuitry in the PLD. For example, the HSSI circuitry is preferably located along one side of the device, taking the place of regular peripheral IO circuitry in that area. Certain portions of the core logic circuitry are modified to better interface with the HSSI circuitry.

Abstract: High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.

Abstract: Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

Abstract: Circuitry for distributing signals such as reference clock signals among blocks of transceiver circuitry on an integrated circuit such as a field programmable gate array (“FPGA”) employs bidirectional buffers rather than unidirectional buffers. This allows all buffers to have the same construction regardless of physical location, which facilitates construction of the circuitry using identical or substantially identical modules. The same approach may be used for distributing other types of signals among the transceiver blocks. For example, this approach may be used for distributing calibration control signals.

Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate activation voltage is higher in voltage than a nominal voltage being supplied to circuitry other than the passgate structures.

Abstract: A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.

Abstract: Circuitry for distributing clock signals (e.g., reference clock signals) among a plurality of blocks of circuitry. Each block may include reference clock source circuitry and reference clock utilization circuitry. Each block also preferably includes an identical or substantially identical module of clock signal distribution circuitry that can (1) accept a signal from the source circuitry in that block, (2) apply any of several clock signals to the utilization circuitry in that block, and (3) connect to the similar module(s) of one or more adjacent blocks.