Abstract: A merchandiser including a case that has an air inlet and defines a product display area with a customer access opening. The merchandiser also includes a canopy that has a first air outlet and a second air outlet, a first passageway connecting the air inlet with the first air outlet to direct a first airflow through the first air outlet at least partially across the opening to define a primary air curtain, and a second passageway in fluid communication with a HVAC system by ducting coupled between the merchandiser and the HVAC system to direct a second airflow defining a secondary air curtain from the HVAC system through the second air outlet at least partially across the opening. The primary and secondary air curtains cooperate with each other to minimize infiltration of ambient air into the product display area.

Abstract: A refrigerated merchandiser including a case that defines a product display area with an opening. The case includes a base that has an air inlet located adjacent the product display area. The refrigerated merchandiser also includes a canopy that is disposed substantially above the product display area, and that has an air outlet located adjacent the product display area. A primary passageway fluidly connects the air inlet with the air outlet to direct a first refrigerated airflow from the air outlet across the opening. The refrigerated merchandiser further includes a shelf coupled to the case within the product display area, and a duct apparatus removably coupled to the shelf and in direct fluid communication with the primary passageway. The duct apparatus defines a secondary air passageway between the primary passageway and the product display area to direct a second refrigerated airflow from the duct apparatus across the opening below the canopy.

Abstract: A door for a refrigerated merchandiser defining a product display area. The door includes a first glass panel, a second glass panel, and a third glass panel. The first glass panel is in communication with an environment surrounding the merchandiser, and has a first surface facing the environment and a second surface opposite the first surface. The second glass panel has a third surface facing the second surface and a fourth surface opposite the third surface. The third glass panel is in communication with the product display area, and has a fifth surface that faces the fourth surface and a sixth surface that is opposite the fifth surface. The door also includes a film that has a split silver low-emissivity coating covering at least a portion of one or more of the first glass panel, the second glass panel, and the third glass panel.

Abstract: A merchandiser that includes a case that defines a product display area and that includes a frame having mullions. The mullions define at least one opening such that the food product within the product display area is accessible from the front of the case. The merchandiser also includes at least one shelf for supporting and displaying food product within the product display area, and a light assembly that is coupled to at least one of the mullions and that is positioned to illuminate the food product. The light assembly includes a first LED that has a first viewing angle and a second LED that has a second viewing angle that is smaller than the first viewing angle.

Abstract: The core of this invention is the application of a fast comparison circuit to the problem of address translation. Traditional implementations generate the virtual address and the physical address in series. This invention generates the physical address and virtual address simultaneously. A bitwise operation on the base address, the offset address and each stored virtual address determines whether the base address and offset address sum equals the virtual address without requiring a carry propagate. Circular addressing is implemented in the match determination by masking bits corresponding to the circular address limit.

Abstract: This invention tracks emulation changes in the program counter of the central processing unit of a data processor during emulation halt. The sequence includes: pausing the central processing unit in response to an emulation halt; employing the emulator to change the program counter. In this case when the central processing unit resumes operation, there will be a discontinuity in the program counter. The trace data will show a change in the program counter address. This invention uses a unique exception signal similar to those used to mark interrupts to inform the user that this program counter discontinuity is due to an emulation change of the program counter during emulation halt.

Abstract: The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.

Abstract: A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.

Abstract: A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon detection of an interrupt. The interrupt during debug bit has a first digital state if the central processing unit is in a debug halt state and a second digital state if the central processing unit is not in a debug halt state. Upon return from an interrupt the central processing unit enter a debug halt state if the interrupt during debug bit has the first state. The return address and the interrupt during debug bit can be embodied in a push-pop stack. The interrupt during debug bit register can be an unused least significant bit of the return address.

Abstract: An instruction-programmable processor, such as a digital signal processor, having a level one program cache memory and instruction buffer subsystem, is disclosed. The subsystem includes a loop cache subsystem that includes a branch cache register file for storing instruction opcodes corresponding to a sequence of fetch addresses beginning with a base address. If the fetch address issued by the instruction fetch unit is a hit relative to the loop cache subsystem loop cache control logic disables reads from program data RAM in favor of accesses to the branch cache register file. The branch cache register file can be loaded with opcodes beginning with each backward branch that is a miss relative to the branch cache register file and can be loaded with opcodes beginning with backward branches that are a miss relative to the branch cache register file and that have been executed twice in succession.

Abstract: A data processing system is provided with a digital signal processor which has an instruction for conditionally branching based on the contents of a specified test register. Each time a branch is taken, the register is decremented as a side effect of executing the branch instruction. In addition, a predicate register is specified by the instruction. A branch occurs only if both registers meet specified conditions.

Abstract: A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon detection of an interrupt. The interrupt during debug bit has a first digital state if the central processing unit is in a debug halt state and a second digital state if the central processing unit is not in a debug halt state. Upon return from an interrupt the central processing unit enter a debug halt state if the interrupt during debug bit has the first state. The return address and the interrupt during debug bit can be embodied in a push-pop stack. The interrupt during debug bit register can be an unused least significant bit of the return address.

Abstract: This invention tracks emulation changes in the program counter of the central processing unit of a data processor during emulation halt. The sequence includes: pausing the central processing unit in response to an emulation halt; employing the emulator to change the program counter. In this case when the central processing unit resumes operation, there will be a discontinuity in the program counter. The trace data will show a change in the program counter address. This invention uses a unique exception signal similar to those used to mark interrupts to inform the user that this program counter discontinuity is due to an emulation change of the program counter during emulation halt.

Abstract: This invention enables a program controlled cache state operation on a program designated address range. The program controlled cache state operation could be writeback of data cached from the program designated address range to a higher level memory or such writeback and invalidation of data cached from the program designated address range. A cache operation unit includes a base address register and a word count register loadable by the central processing unit. The program designated address range is from a base address for a number of words of the word count register. In the preferred embodiment the program controlled cache state operation begins upon loading the word count register. The cache operation unit may operate on fractional cache entries by handling misaligned first and last cycles. Alternatively, The cache operation unit may operate only on whole cache entries. The base address register increments and the word count register decrements until when the word count reaches zero.

Abstract: A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of ways as directly addressable memory and configuring remaining ways as cache memory. Control logic inhibits indication that tag bits matches address bits and that a cache entry is the least recently used for cache eviction if the corresponding way is configured as directly addressable memory. In an alternative embodiment, the memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of sets equal to 2M, where M is an integer, as cache memory and configuring remaining sets as directly addressable memory.

Abstract: A data processing apparatus includes a data processor core having integral cache memory and local memory, and external memory interface and a direct memory access unit. The direct memory access unit is connected to a single data interchange port of the data processor core and to an internal data interchange port of the external memory interface. The direct memory access unit transports data according to commands received from the data processor core to or from devices external to the data processing unit via the external memory interface. As an extension of this invention, a single direct memory access unit may serve a multiprocessing environment including plural data processor cores. The data processor core, external memory interface and direct memory access unit are preferably embodied in a single integrated circuit. The data processor core preferably includes an instruction cache for temporarily storing program instructions and a data cache for temporarily storing data.

Abstract: A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline procedure can be terminated early. An interrupt state is provided to permit the servicing of an interrupt.

Abstract: A program memory controller unit includes apparatus for the execution of a software pipeline loop procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline procedure can be terminated early. A second software procedure can be initiated prior to the completion of first software procedure. An SPEXIT instruction is provided to permit the software pipeline program to terminate upon the identification of a preselected condition. The SPEXIT instruction is placed in the instruction sequence to insure that response to the instruction occurs after the prolog procedure has been completed. The SPEXIT instruction, upon identification of the preselected condition, results in the software pipeline loop procedure entering an idle state.

Abstract: A data processing system (1300) is provided with a digital signal processor (DSP) (1301) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm processing. The DSP has dual load/store units (.D1, .D2) connected to dual memory ports (T1, T2) in a level one data cache memory controller (1720a). The DSP can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The DSP can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports.

Abstract: A data processing system having a central processing unit, at least one level one cache, a level two unified cache, a directly addressable memory and a direct memory access unit includes a snoop unit generating snoop accesses to the at least one level one cache upon a direct memory access to the directly addressable memory. The snoop unit generates a write snoop access to both level one caches upon a direct memory access write to or a direct memory access read from the directly addressable memory. The level one cache also invalidates a cache entry upon a snoop hit and also writes back a dirty cache entry to the directly addressable memory. A level two memory is selectively configurable as part level two unified cache and part directly addressable memory.