Patents by Inventor Timothy D. Anderson

Timothy D. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation
    Patent number: 9582273
    Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: February 28, 2017
    Assignee: TEXAS INSTRMENTS INCORPORATED
    Inventors: Mujibur Rahman, Djordje Senicic, Timothy D. Anderson
  • Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors
    Patent number: 9557936
    Abstract: This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: January 31, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy D. Anderson, Joseph Zbiciak, Abhijeet A. Chachad, Kai Chirca, Naveen Bhoria, David M. Thompson, Jonathan (Son) Hung Tran, Ramakrishnan Venkatasubramanian
  • MERCHANDISER WITH AIRFLOW DIVIDER
    Publication number: 20170013973
    Abstract: A fan plenum for a refrigerated merchandiser, in which the refrigerated merchandiser includes a case defining a product display area and a lower flue, a first air passageway, and a second air passageway, and in which the first air passageway and second air passageway are in fluid communication with the lower flue and with the product display area, includes a top wall including a fan aperture for receiving a fan having a plurality of fan blades. The fan plenum further includes a side wall and a plenum base. An airflow divider partitions the fan plenum into a first duct and a second duct. The first duct is fluidly couplable with the first air passageway and the second duct is fluidly couplable with the second air passageway.
    Type: Application
    Filed: September 29, 2016
    Publication date: January 19, 2017
    Inventors: Ken Nguyen, Timothy D. Anderson
  • Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
    Patent number: 9489314
    Abstract: This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: November 8, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew D. Pierson, Timothy D. Anderson
  • Multi domain bridge with auto snoop response
    Patent number: 9489307
    Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The powerdown mechanism is isolated to just the asynchronous bridge implemented between the master and the interconnect with a basic request/acknowledge handshake between the master subsystem and the asynchronous bridge.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: November 8, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daniel B Wu, Timothy D Anderson
  • Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
    Patent number: 9465767
    Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 11, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew D Pierson, Daniel B Wu, Timothy D Anderson
  • Multi processor multi domain conversion bridge with out of order return buffering
    Patent number: 9465741
    Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: October 11, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Daniel B Wu, Matthew D Pierson, Timothy D. Anderson
  • Door for a refrigerated merchandiser
    Patent number: 9462896
    Abstract: A door for a refrigerated merchandiser defining a product display area. The door includes a first glass panel, a second glass panel, and a third glass panel. The first glass panel is in communication with an environment surrounding the refrigerated merchandiser, and has a first surface arranged to face the environment and a second surface opposite the first surface. The second glass panel is positioned adjacent the first glass panel, and has a third surface arranged to face the second surface and a fourth surface opposite the third surface. The third glass panel is positioned adjacent the second glass panel and is in communication with the product display area. The third glass panel has a fifth surface arranged to face the fourth surface and a sixth surface opposite the fifth surface and arranged to face the product display area.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: October 11, 2016
    Assignee: Hussmann Corporation
    Inventors: Craig S. Reichert, Timothy D. Anderson
  • Merchandiser with airflow divider
    Patent number: 9456706
    Abstract: A refrigerated merchandiser includes a case defining a product display area and having a base, a lower flue, a first air passageway, and a second air passageway. The first air passageway and second air passageway are in fluid communication with the lower flue and with the product display area. The refrigerated merchandiser also includes an evaporator positioned in the first air passageway and a fan assembly positioned in the base in fluid communication with the lower flue to generate an airflow. A fan plenum into which the fan assembly is disposed includes an airflow divider to direct a first portion of the airflow to the first air passageway and to direct a second portion of the airflow to the second air passageway. The proportion of air between the first portion and the second portion is a function of the position and geometry of the airflow divider.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 4, 2016
    Assignee: Hussmann Corporation
    Inventors: Ken Nguyen, Timothy D. Anderson
  • Three-term predictive adder and/or subtracter
    Patent number: 9448767
    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: September 20, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy D. Anderson, Mujibur Rahman, Kai Chirca
  • DOOR FOR A EFRIGERATED MERCHANDISER
    Publication number: 20160198866
    Abstract: A door for a refrigerated merchandiser defining a product display area. The door includes a first glass panel, a second glass panel, and a third glass panel. The first glass panel is configured to be in communication with an environment surrounding the refrigerated merchandiser, and has a first surface arranged to face the environment and a second surface opposite the first surface. The second glass panel is positioned adjacent the first glass panel, and has a third surface arranged to face the second surface and a fourth surface opposite the third surface. The third glass panel is positioned adjacent the second glass panel and is configured to be in communication with the product display area. The third glass panel has a fifth surface arranged to face the fourth surface and a sixth surface opposite the fifth surface and arranged to face the product display area.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Craig S. Reichert, Timothy D. Anderson
  • Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
    Patent number: 9372799
    Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: June 21, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daniel B Wu, Matthew D Pierson, Kai Chirca, Timothy D Anderson
  • Door for a refrigerated merchandiser
    Patent number: 9289079
    Abstract: A door for a refrigerated merchandiser defining a product display area. The door includes a first glass panel, a second glass panel, and a third glass panel. The first glass panel is in communication with an environment surrounding the merchandiser, and has a first surface facing the environment and a second surface opposite the first surface. The second glass panel has a third surface facing the second surface and a fourth surface opposite the third surface. The third glass panel is in communication with the product display area, and has a fifth surface that faces the fourth surface and a sixth surface that is opposite the fifth surface. The door also includes a film that has a split silver low-emissivity coating covering at least a portion of one or more of the first glass panel, the second glass panel, and the third glass panel.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: March 22, 2016
    Assignee: Hussmann Corporation
    Inventors: Craig S. Reichert, Timothy D. Anderson
  • Multi-Processor, Multi-Domain, Multi-Protocol Cache Coherent Speculation Aware Shared Memory Controller and Interconnect
    Publication number: 20160055096
    Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
    Type: Application
    Filed: November 3, 2015
    Publication date: February 25, 2016
    Inventors: Kai Chirca, Matthew D Pierson, Daniel B Wu, Timothy D Anderson
  • Pipeline liner monitoring system
    Patent number: 9267635
    Abstract: A pipeline monitoring system and systems and methods of producing the same. A system for producing a liner for a pipe can comprise a source of material to form a body of the liner and a source of material to form a monitoring sensor in the liner. The system may further comprise a device that receives the material to form the body of the liner and the material to form the monitoring sensor in the liner and produces the body of the liner with the monitoring sensor embedded within the body of the liner.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 23, 2016
    Assignee: ExxonMobil Upstream Research Company
    Inventors: Mohan G. Kulkarni, Timothy D. Anderson
  • Compiler-control method for load speculation in a statically scheduled microprocessor
    Patent number: 9239735
    Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: January 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy D. Anderson, Joseph Zbiciak, Duc Q. Bui, Mel A. Phipps, Todd T. Hahn
  • Prefetcher with arbitrary downstream prefetch cancelation
    Patent number: 9239798
    Abstract: A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: January 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew D Pierson, Joseph R M Zbiciak, Kai Chirca, Amitabh Menon, Timothy D Anderson
  • Merchandiser with airflow divider
    Patent number: 9220354
    Abstract: A refrigerated merchandiser includes a case defining a product display area and having a base, a lower flue, a first air passageway, and a second air passageway. The first air passageway and second air passageway are in fluid communication with the lower flue and with the product display area. A fan plenum has an outlet defining a first plane. A second plane is defined perpendicular to the first plane and passing through the center of a fan aperture. The fan plenum further includes an airflow divider with a first wall member and a second wall member positioned to direct a first portion of the airflow to the first air passageway and a second portion of the airflow to the second air passageway. The space between the first wall member and the second wall member defines an area, the greater portion of which is to one side of the second plane.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: December 29, 2015
    Assignee: Hussmann Corporation
    Inventors: Ken Nguyen, Timothy D. Anderson
  • OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION
    Publication number: 20150370710
    Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.
    Type: Application
    Filed: September 1, 2015
    Publication date: December 24, 2015
    Inventors: Daniel B. Wu, Matthew D. Pierson, Kai Chirca, Timothy D. Anderson
  • Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
    Patent number: 9208120
    Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: December 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew D. Pierson, Daniel B. Wu, Timothy D. Anderson