Abstract: The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2?b2+c2) with (x2+y2+z2); and (a3+b3?c3) with (x3+y3+z3); implementing an efficient method of computing (a4?b4?c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract: This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. This invention initiates a snoop cycle based upon the address of the coherence write. The stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.

Abstract: A method of controlling a refrigerated merchandiser including a plurality of display case modules each having a separate refrigeration circuit with a compressor and an evaporator. The method includes selectively starting and stopping a first compressor of a first refrigeration circuit having a first evaporator associated with a first display case module to regulate a temperature in a product display area of the first display case module, and selectively starting and stopping a second compressor of a second refrigeration circuit having a second evaporator associated with a second display case module to regulate a temperature in a product display area of the second display case module. The method also includes controlling the first refrigeration module and the second refrigeration module based on a heat load of the merchandiser and a predetermined number of start/stop cycles of each of the first compressor and the second compressor within a given time period.

Abstract: A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined in response to a prefetch address stored in a slot of an array for storing portions of predicted addresses and associated with a slot in accordance with an order in which a prefetch FIFO counter is modified to select the slots of the array. Data is prefetched from a lower-level hierarchical memory in accordance with a next predicted address and provisioned the prefetched data to minimize a read time for reading the prefetched data. The provisioned prefetched data is read-out when the address of the memory request is associated with the next predicted address.

Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

Abstract: A prefetch filter receives a memory read request having an associated address for accessing data that is stored in a line of memory. An address window is determined that has an address range that encompasses an address space that is twice as large as the line of memory. In response to a determination of in which half the address window includes the requested line of memory, a prefetch direction is to a first direction or to an opposite direction. The prefetch filter can include an array of slots for storing a portion of a next predicted access and determine a memory stream in response to a hit on the array by a subsequent memory request. The prefetch filter FIFO counter cycles through the slots of the array before wrapping around to a first slot of the array for storing a next predicted address portion.

Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.

Abstract: A reinforced pipeline liner designed to facilitate installation and systems and methods for producing and installing a reinforced pipeline liner. A reinforced pipeline liner can comprise a body portion having a layer of matrix material, the layer having an inner surface and an outer surface, and a plurality of interspersed reinforcement structures embedded within the body portion. The reinforcement structures are positioned between the inner surface and outer surface of the layer and circumferentially offset from the other reinforcement structures. Additionally, the body portion may have multiple thicknesses.

Abstract: A merchandiser including a case defining a product display area and having case structure. The merchandiser also includes a light assembly. The light assembly has a light housing and a light source coupled to the light housing to direct light generally toward the product display area. The merchandiser further includes an attachment mechanism having a magnet housing and a magnet substantially enclosed by the magnet housing. The attachment mechanism is coupled to the light housing opposite the light source to attach the light assembly to the case structure.

Abstract: A merchandiser including a case that defines a product display area. The case includes a canopy that has a first air outlet in fluid communication with a primary air passageway within the case to direct a primary air curtain into the product display area, and a second air outlet in fluid communication with a secondary air passageway within the case to direct a secondary air curtain into the product display area. The merchandiser also includes a divider that is coupled to the canopy between the primary air passageway and the secondary air passageway. The divider provides airflow communication between the primary air passageway and the secondary air passageway upstream of the first and second air outlets.

Abstract: A pipeline monitoring system and systems and methods of producing the same. A system for producing a liner for a pipe can comprise a source of material to form a body of the liner and a source of material to form a monitoring sensor in the liner. The system may further comprise a device that receives the material to form the body of the liner and the material to form the monitoring sensor in the liner and produces the body of the liner with the monitoring sensor embedded within the body of the liner.

Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space.

Abstract: A processor includes a shift device for extending the width of a rotator without increasing propagation delays. An extended-width result is obtained by combining a rotation result with a shift result in accordance with a mask that is selected in response to at least a portion of the value of the degree to which a data word is to be shifted.

Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract: This invention is a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

Abstract: An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.