Abstract: An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.

Abstract: Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

Abstract: A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

Abstract: A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.

Abstract: Chip connection structures and related methods of forming such structures are disclosed. In one case, an interconnect structure is disclosed, the structure including: a pillar connecting an integrated circuit chip and a substrate, the pillar including a barrier layer, a first copper layer over the barrier layer, and a first solder layer over the first copper layer.

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

Abstract: The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure.

Abstract: The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure.

Abstract: Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.

Abstract: Structures are provided with raised buffer pads for solder bumps. Methods are also provided for forming the raised buffer pads for solder bumps. The method includes forming a raised localized buffer pad structure on a tensile side of a last metal layer of a solder bump connection. The raised localized buffer pad structure increases a height of a portion of a pad structure of the solder bump connection with respect to a compressive side of the last metal layer.

Abstract: A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.

Abstract: Pillar interconnect chip to package and global wiring structures and methods of manufacturing are discloses. The method includes forming a resist directly over at least one landing pad and at least one wiring layer, and forming a first pattern in the resist over the landing pad and a second pattern over the wiring layer, using a single lithography step. The method further includes forming metal in the first pattern in electrical contact with the landing pad. The method further includes removing remaining resist over the wiring layer to deepen the second pattern. The method further includes forming a pillar interconnect in the first pattern and a wiring in the second pattern by adding additional metal on the metal in the first pattern and over the at least one wiring layer in the second pattern, respectively. The method further includes removing any remaining resist.

Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.

Abstract: A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.

Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.

Abstract: A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.

Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.

Abstract: A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars.