Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.

Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.

Abstract: A bias circuit for a capacitive sensor may include a variable impedance element coupled to a capacitor of the capacitive sensor wherein an impedance of the variable impedance element is varied in accordance with a temperature associated with the bias circuit and an active feedback circuit coupled between the variable impedance element and an output of a processing circuit for processing a signal generated by the capacitive sensor and configured to drive the variable impedance element to force a direct-current (DC) voltage level of an output of the capacitive sensor to a desired voltage.

Abstract: A bias circuit for a capacitive sensor may include a variable impedance element coupled to a capacitor of the capacitive sensor wherein an impedance of the variable impedance element is varied in accordance with a temperature associated with the bias circuit and an active feedback circuit coupled between the variable impedance element and an output of a processing circuit for processing a signal generated by the capacitive sensor and configured to drive the variable impedance element to force a direct-current (DC) voltage level of an output of the capacitive sensor to a desired voltage.

Abstract: The charge drawn from a battery during each switching event (pulse) of a pulse frequency modulated DC-DC converter is determined during a calibration period. based on differences in pulse rate with different current loading. Another approach calibration approach determines charge drawn from the battery by measuring voltage across a sense resistor while measuring the total pulse rate and while adding sufficient load current to ensure that the voltage is much larger than the residual offset of the measurement system. During operation, the system counts number of pulses are counted and the total charge drawn from the battery is determined based, at least in part, on the charge transferred per pulse during calibration, the operational mode, the battery voltage during calibration and operationally and the output voltage. Based on the total charge drawn and temperature (for temperature dependent battery types), the battery state of charge is estimated.

Abstract: The charge drawn from a battery during each switching event (pulse) of a pulse frequency modulated DC-DC converter is determined during a calibration period. based on differences in pulse rate with different current loading. Another approach calibration approach determines charge drawn from the battery by measuring voltage across a sense resistor while measuring the total pulse rate and while adding sufficient load current to ensure that the voltage is much larger than the residual offset of the measurement system. During operation, the system counts number of pulses are counted and the total charge drawn from the battery is determined based, at least in part, on the charge transferred per pulse during calibration, the operational mode, the battery voltage during calibration and operationally and the output voltage. Based on the total charge drawn and temperature (for temperature dependent battery types), the battery state of charge is estimated.

Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.

Abstract: An apparatus for communicating using an isolation channel includes a transmitter circuit having a first terminal configured to communicate a first signal. The first signal oscillates in response to a data signal having a first signal level and is constant in response to the data signal having a second signal level. The transmitter circuit includes a second terminal configured to communicate that oscillates in response to the data signal having the second signal level and is constant in response to the data signal having the first signal level. The apparatus may include a receiver circuit configured to generate a recovered data signal having a first transition in a first direction between first and second levels based on an edge of a first received signal and having a second transition in a second direction between the first and second levels based on an edge of a second received signal.

Abstract: An isolated power transfer device includes a transformer formed in a multi-layer substrate of an integrated circuit package. A primary winding of the transformer is coupled to a first integrated circuit to form a DC/AC power converter and a secondary winding of the transformer is coupled to a second integrated circuit to form an AC/DC power converter. The first and second integrated circuits are electrically isolated from each other. The first integrated circuit includes a lightly doped drain MOSFET integrated with conventional CMOS devices and the second integrated circuit includes a Schottky diode integrated with conventional CMOS devices. The isolated power transfer device includes a capacitive channel for communication of information across an isolation barrier from the second integrated circuit to the first integrated circuit. Capacitors of the capacitive channel may be formed in the multi-layer substrate of the integrated circuit package.

Abstract: A die is mounted in an integrated circuit package. The die includes a balun circuit and an electrostatic discharge (ESD) circuit coupled to a ground of the integrated circuit die. The package has a first output pin coupled to a first terminal of the balun and has a second output pin coupled to a second terminal of the balun through first and second bond wires. The second output pin is connected to board ground. A third bond wire is disposed between the second package terminal and the ESD circuit to provide a safe discharge path through the third bond wire for ESD events affecting the first and second output terminals. Thus, a charge that builds up involving one of the output terminals coupled to the balun can be safely dissipated.

Abstract: An oscillator supplies a clock signal having a frequency determined in part according to a received current. A transmit side charge pump is coupled to the clock signal and boosts a voltage supplied to the charge pump to generate a boosted voltage. A driver circuit drives a transmit signal having a frequency based on the clock signal and a voltage based on the boosted voltage to a capacitive isolation communication path. A receive side charge pump is coupled to the isolation capacitors of the isolation communication path and boosts a voltage of the received signal on the receive side of the isolation communication path and supplies a gate signal with the boosted voltage to a gate of at least one transistor.

Abstract: An oscillator supplies a clock signal having a frequency determined in part according to a received current. A transmit side charge pump is coupled to the clock signal and boosts a voltage supplied to the charge pump to generate a boosted voltage. A driver circuit drives a transmit signal having a frequency based on the clock signal and a voltage based on the boosted voltage to a capacitive isolation communication path. A receive side charge pump is coupled to the isolation capacitors of the isolation communication path and boosts a voltage of the received signal on the receive side of the isolation communication path and supplies a gate signal with the boosted voltage to a gate of at least one transistor.

Abstract: A die is mounted in an integrated circuit package. The die includes a balun circuit and an electrostatic discharge (ESD) circuit coupled to a ground of the integrated circuit die. The package has a first output pin coupled to a first terminal of the balun and has a second output pin coupled to a second terminal of the balun through first and second bond wires. The second output pin is connected to board ground. A third bond wire is disposed between the second package terminal and the ESD circuit to provide a safe discharge path through the third bond wire for ESD events affecting the first and second output terminals. Thus, a charge that builds up involving one of the output terminals coupled to the balun can be safely dissipated.

Abstract: Common mode transient immunity for an isolation system is improved by using a common transient suppression circuit coupled to a receive circuit to suppress transients in signals received by the receive circuit that were transmitted from a transmit side of the isolation barrier using optical, magnetic, inductive, or other mechanisms.

Abstract: Common mode transient immunity for an isolation system is improved by using a common transient suppression circuit coupled to a receive circuit to suppress transients in signals received by the receive circuit that were transmitted from a transmit side of the isolation barrier using optical, magnetic, inductive, or other mechanisms.

Abstract: An apparatus for communicating using an isolation channel includes a transmitter circuit having a first terminal configured to communicate a first signal. The first signal oscillates in response to a data signal having a first signal level and is constant in response to the data signal having a second signal level. The transmitter circuit includes a second terminal configured to communicate that oscillates in response to the data signal having the second signal level and is constant in response to the data signal having the first signal level. The apparatus may include a receiver circuit configured to generate a recovered data signal having a first transition in a first direction between first and second levels based on an edge of a first received signal and having a second transition in a second direction between the first and second levels based on an edge of a second received signal.

Abstract: An apparatus includes a regulator circuit that generates a voltage in response to an input current being supplied to an input terminal and functional circuitry, powered by the voltage generated by the regulator circuit. The functional circuitry, e.g., an oscillator, generates a signal using the generated voltage, the signal indicative that the current is being supplied to the apparatus. The signal can be provided over an isolation link to provide a control signal for controlling a high voltage driver circuit.

Abstract: ESD (electrostatic discharge) protection for radio frequency (RF) couplers included in the same semiconductor package as other integrated circuits, such as integrated circuits having power amplifier (PA) circuitry, is disclosed along with related systems and methods. The disclosed embodiments provide ESD protection for RF couplers within semiconductor packages by including coupler ESD circuitry within an integrated circuit within the semiconductor package and coupling the connection ports of the RF coupler to this coupler ESD circuitry. Further, this coupler ESD circuitry can be implemented using two sets of serially connected diodes so that the signal connected to the coupler ESD circuitry can swing around ground without being clipped by the ESD circuitry. Still further, the ESD diodes can be formed in deep N well structures to improve isolation and to reduce parasitic capacitance associated with the ESD diodes.

Abstract: Delivered power detection for power amplifiers (PAs) and related systems and methods are disclosed. The disclosed embodiments and techniques provide a delivered power indication for systems using PAs, including such systems for cellular telephone applications, allow power detection circuitry to be integrated on the same integrated circuit die as the PA, and provide power detection circuitry with output signals at baseband frequencies. In one embodiment, the delivered power detection circuitry includes output voltage level detection circuitry and output current level detection circuitry that provide current signals to multiplier circuitry, which in turn provides current output signals proportional to the actual delivered power to the load as represented by the incident power to the load reduced by the reflected power.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.