Patents by Inventor Timothy J. Dupuis

Timothy J. Dupuis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6289070
    Abstract: A digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the ADC offset signal during normal operation of the isolation barrier system. The offset calibration system includes a coarse offset signal generator which provides ;elected increments of offset voltage to the ADC outside of the outgoing data signal channel, In order to increase the calibration range and to avoid injecting large offset voltages into the outgoing data channel. Fixed bias signals are also provided for the ADC and for a DAC in the system.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: September 11, 2001
    Assignee: Silicon Laboratories, Inc.
    Inventors: Andrew W. Krone, Timothy J. Dupuis, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6201865
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided that has switchable time constants. A first time constant may be utilized during a first operation phase immediately after off-hook conditions to allow for fast settling times. Then, a second operation phase is entered in which a second time constant may be utilized. During the second operation phase the DC holding circuit operates slower to create improved low frequency performance.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: March 13, 2001
    Assignee: Silicon Laboratories, Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6144326
    Abstract: A digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the ADC offset signal during normal operation of the isolation barrier system. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: November 7, 2000
    Assignee: Silicon Laboratories, Inc.
    Inventors: Andrew W. Krone, Timothy J. Dupuis, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 5824936
    Abstract: A linear approximation to an exponential decay function exploits the characteristic of an exponential function that, at equal time intervals, the ratio of a parameter value at the beginning of the interval to the parameter value at the end of the interval remains constant. The technique for linear approximation of an exponential decay includes selection of a constant period or interval of time and selection of a constant ratio between the parameter value at the beginning of the constant period and the parameter value at the end of the constant period. In one embodiment, the selected ratio is one-half to exploit a binary arithmetic implementation. For a ratio of one-half, the exponential decay has a "half-life" in which only half the parameter value at the beginning of a period is left at the end of the selected "half-life time period".
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: October 20, 1998
    Assignee: Crystal Semiconductor Corporation
    Inventors: Timothy J. DuPuis, Melita Jaric
  • Patent number: 5397944
    Abstract: An audio mixer circuit on an integrated circuit chip performs a calibration operation on power up which calibrates out most of the offset voltages of the operational amplifiers used in the mixer. The calibration logic includes a shared calibrate circuit which provides timing signals to each operational amplifier and its associated calibration circuitry. The calibration operation is performed by digitally controlling and changing the bias current into each of the operational amplifiers until the offset voltage is compensated. A class A flip-flop circuit is used in the digital counter of the calibration circuitry to drive a current digital-to-analog converter.
    Type: Grant
    Filed: April 9, 1993
    Date of Patent: March 14, 1995
    Assignee: Crystal Semiconductor Corporation
    Inventor: Timothy J. DuPuis