Abstract: A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife.

Abstract: A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

Abstract: A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed as a reconstituted wafer. A plurality of unit specific patterns can be formed by forming a unit specific pattern over each of the plurality of semiconductor die, wherein each of the unit specific patterns is customized to fit its respective semiconductor die. A plurality of images can be acquired by acquiring an image for each of the plurality of unit specific patterns. A plurality of unique reference standards can be created by creating a unique reference standard for each of the plurality of unit specific patterns. Defects can be detected in the plurality of unit specific patterns by comparing one of the plurality of unique reference standards to a corresponding one of the plurality of images for each of the plurality of unit specific patterns.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed as a reconstituted wafer. A plurality of unit specific patterns can be formed by forming a unit specific pattern over each of the plurality of semiconductor die, wherein each of the unit specific patterns is customized to fit its respective semiconductor die. A plurality of images can be acquired by acquiring an image for each of the plurality of unit specific patterns. A plurality of unique reference standards can be created by creating a unique reference standard for each of the plurality of unit specific patterns. Defects can be detected in the plurality of unit specific patterns by comparing one of the plurality of unique reference standards to a corresponding one of the plurality of images for each of the plurality of unit specific patterns.

Abstract: A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed as a reconstituted wafer. A plurality of unit specific patterns can be formed by forming a unit specific pattern over each of the plurality of semiconductor die, wherein each of the unit specific patterns is customized to fit its respective semiconductor die. A plurality of images can be acquired by acquiring an image for each of the plurality of unit specific patterns. A plurality of unique reference standards can be created by creating a unique reference standard for each of the plurality of unit specific patterns. Defects can be detected in the plurality of unit specific patterns by comparing one of the plurality of unique reference standards to a corresponding one of the plurality of images for each of the plurality of unit specific patterns.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper column disposed over the active surface of each semiconductor die is provided. An embedded die panel is formed by disposing an encapsulant around each of the plurality of semiconductor die. A true position and rotation of each semiconductor die within the embedded die panel is measured. A unit-specific pattern is formed to align with the true position of each semiconductor die in the embedded die panel. The unit-specific pattern as a fan-out structure disposed over the semiconductor die, over the encapsulant, and coupled to the copper columns. A fan-in redistribution layer (RDL) can extend over the active surface of each semiconductor die such that the copper columns formed over the fan-in RDLs. The unit-specific pattern can be directly coupled to the copper columns.

Abstract: A semiconductor device and method of making a semiconductor device is described. An embedded die panel comprising a plurality of semiconductor die separated by saw streets is provided. A conductive layer is formed by an electroless plating process, the conductive layer comprising bussing lines disposed in the saw streets and a redistribution layer (RDL) coupled to the semiconductor die and bussing lines. An insulating layer is formed over the conductive layer and embedded die panel, the insulating layer comprising openings disposed over the conductive layer outside a footprint of the semiconductor die. Interconnect structures are formed in the openings in the insulating layer by using the conductive layer as part of an electroplating process. The embedded die panel is singulated through the saw streets after forming the interconnect structures to remove the bussing lines and to from individual fan-out wafer level packages (FOWLPs).

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper column disposed over the active surface of each semiconductor die is provided. An embedded die panel is formed by disposing an encapsulant around each of the plurality of semiconductor die. A true position and rotation of each semiconductor die within the embedded die panel is measured. A unit-specific pattern is formed to align with the true position of each semiconductor die in the embedded die panel. The unit-specific pattern as a fan-out structure disposed over the semiconductor die, over the encapsulant, and coupled to the copper columns. A fan-in redistribution layer (RDL) can extend over the active surface of each semiconductor die such that the copper columns formed over the fan-in RDLs. The unit-specific pattern can be directly coupled to the copper columns.

Abstract: A semiconductor device and method of making a semiconductor device is described. An embedded die panel comprising a plurality of semiconductor die separated by saw streets is provided. A conductive layer is formed by an electroless plating process, the conductive layer comprising bussing lines disposed in the saw streets and a redistribution layer (RDL) coupled to the semiconductor die and bussing lines. An insulating layer is formed over the conductive layer and embedded die panel, the insulating layer comprising openings disposed over the conductive layer outside a footprint of the semiconductor die. Interconnect structures are formed in the openings in the insulating layer by using the conductive layer as part of an electroplating process. The embedded die panel is singulated through the saw streets after forming the interconnect structures to remove the bussing lines and to from individual fan-out wafer level packages (FOWLPs).

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a concentrated photovoltaic receiver package or module. In each embodiment of the present invention, the module comprises a leadframe including a first section and a second section disposed in spaced relation to each other. Mounted to the first section of the leadframe is a receiver die. The receiver die is electrically connected to both the first and second sections of the leadframe. In one embodiment of the present invention, the receiver die is electrically connected to the second section of the leadframe by a plurality of conductive wires. In another embodiment of the present invention, the receiver die is electrically connected to the second section of the leadframe by a conductive bonding material. Portions of the leadframe may optionally be covered by a molded body which can be used to define an alignment feature for a light concentrating device such as a light guide or optical rod.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: A carrier provides the ability to perform wet chemical processing on substrates using low cost equipment inspired by the electroplating methods typically utilized in leadframe-based semiconductor packaging or printed circuit board industries. Two frame pieces are mated together to form the carrier which enables transport of at least one substrate through wet chemical processing and includes a non-conductive frame with an exposed conductive flange to allow electrical coupling with processing equipment. Electrical contacts within the non-conductive frame make contact with the at least one substrate and are coupled to the conductive flange allowing an electrical potential to develop across the substrate while undergoing processing within the electroplating equipment.

Abstract: In accordance with the present invention, there are provided multiple embodiments of a semiconductor package, each embodiment including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, each embodiment of the semiconductor package of the present invention includes a generally planar die pad and a plurality of leads. Some of these leads include exposed bottom surface portions or lands which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. A passive device may be electrically connected to and extend between the die pad and one of the leads, and/or may be electrically connected to and extend between and adjacent pair of the leads.

Abstract: In accordance with the present invention, there are provided multiple embodiments of a semiconductor package, each embodiment including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, each embodiment of the semiconductor package of the present invention includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads, the exposed portions of the bottom surfaces of which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of both rows thereof being exposed in a common exterior surface of the package body.