Abstract: A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

Abstract: A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

Abstract: A multi-step conductive interconnect (MSI) may comprise a first step of the MSI comprising a first end and a second end opposite the first end, a first height (Ha) and a first diameter (Da). A second step of the MSI may comprise a first end and a second end opposite the first end. The first end of the second step contacts the second end of the first step. The second step may comprise a second height (Hb) and a second diameter (Db). The MSI may comprise a height (H) and a height to width aspect ratio (H:Da) greater than or equal to 1.5:1. A sidewall of the first step may comprise an offset (O) with respect to a sidewall of the second step to form a disjointed sidewall profile. The offset O may be in a range of 0.1 ?m-20 ?m.

Abstract: A semiconductor device may comprise a bridge die comprising copper studs. Copper posts may be disposed in a periphery of the bridge die. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure comprising first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die. The first pitch may be at least 1.5 times less than the second pitch.

Abstract: A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

Abstract: A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.

Abstract: A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.

Abstract: A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.

Abstract: A method of making a semiconductor device can include providing a semiconductor die comprising a front surface comprising a gate pad and a source pad, the semiconductor die further comprising a back surface opposite the front surface, the back surface comprising a drain. A gate stud may be formed over and coupled to the gate pad. A source stud may be formed over and coupled to the source pad. An encapsulant may be formed over the semiconductor die. A through mold interconnect may extend between opposing first and second surfaces of the encapsulant. An RDL may be coupled to the gate stud, the source stud, and to the through mold interconnect. A land pad may be formed over the back surface of the semiconductor die and be coupled to the drain after singulating the semiconductor die from its native wafer and after forming the encapsulant over the semiconductor die.

Abstract: A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife.

Abstract: A method of making a semiconductor device can include providing a semiconductor die comprising a front surface comprising a gate pad and a source pad, the semiconductor die further comprising a back surface opposite the front surface, the back surface comprising a drain. A gate stud may be formed over and coupled to the gate pad. A source stud may be formed over and coupled to the source pad. An encapsulant may be formed over the semiconductor die. A through mold interconnect may extend between opposing first and second surfaces of the encapsulant. An RDL may be coupled to the gate stud, the source stud, and to the through mold interconnect. A land pad may be formed over the back surface of the semiconductor die and be coupled to the drain after singulating the semiconductor die from its native wafer and after forming the encapsulant over the semiconductor die.

Abstract: A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects.

Abstract: A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

Abstract: A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects.

Abstract: An automated optical inspection (AOI) system can comprise aligning a wafer comprising a plurality of unit specific patterns. A plurality of unique reference standards can be created as a plurality of electrical nets by generating with a computer an electrical net for each of the unit specific patterns, each of the plurality of electrical nets comprising a start point and an end point. An image of each of the plurality of unit specific patterns can be captured with a camera. The image can be processed with the computer to provide a plurality of extracted boundaries of contiguous electrically conductive regions. Defects in the plurality of unit specific patterns, if present, can be detected by comparing each of the extracted boundaries of contiguous electrically conductive regions to a corresponding one of the plurality of unique reference standards. An output of known good die can be created.

Abstract: A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper column disposed over the active surface of each semiconductor die is provided. An embedded die panel is formed by disposing an encapsulant around each of the plurality of semiconductor die. A true position and rotation of each semiconductor die within the embedded die panel is measured. A unit-specific pattern is formed to align with the true position of each semiconductor die in the embedded die panel. The unit-specific pattern as a fan-out structure disposed over the semiconductor die, over the encapsulant, and coupled to the copper columns. A fan-in redistribution layer (RDL) can extend over the active surface of each semiconductor die such that the copper columns formed over the fan-in RDLs. The unit-specific pattern can be directly coupled to the copper columns.

Abstract: A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

Abstract: An automated optical inspection (AOI) system can comprise aligning a wafer comprising a plurality of unit specific patterns. A plurality of unique reference standards can be created as a plurality of electrical nets by generating with a computer an electrical net for each of the unit specific patterns, each of the plurality of electrical nets comprising a start point and an end point. An image of each of the plurality of unit specific patterns can be captured with a camera. The image can be processed with the computer to provide a plurality of extracted boundaries of contiguous electrically conductive regions. Defects in the plurality of unit specific patterns, if present, can be detected by comparing each of the extracted boundaries of contiguous electrically conductive regions to a corresponding one of the plurality of unique reference standards. An output of known good die can be created.

Abstract: A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife.