Abstract: A method of making a semiconductor assembly may include providing a semiconductor component disposed within a first encapsulant, the encapsulant being disposed around and contacting at least four side surfaces of the semiconductor component and disposed over frontside of the semiconductor component. A first layered structure may be formed as a build-up interconnect structure over the encapsulant and over the semiconductor component. The first layered structure may comprise a first conductive layer formed over the first encapsulant, a first dielectric formed over the first conductive layer, and a second encapsulant disposed over first conductive layer and over first dielectric. An upper surface of the second encapsulant may be planarized to create a flat surface on which to form additional structures, such as a second layered structure or a package interconnect.

Abstract: A semiconductor assembly includes a bridge component without vias extending through the bridge component. The bridge component includes one or more interconnect layers over a frontside of the bridge and an outermost interconnect layer coupled to conductive studs. Conductive vertical interconnects are in a periphery of the assembly with an encapsulant on five sides of the bridge component, on sides of the conductive studs, and on sides of the conductive vertical interconnects that leave ends of the conductive studs and ends of the conductive vertical interconnects coplanar with top and bottom surfaces of the encapsulant. A frontside build-up interconnect structure is over the conductive studs and couple to first ends of the conductive vertical interconnects. The frontside build-up interconnect includes first pads at a first pitch within a footprint of the bridge component and second pads at a second pitch outside a footprint of the bridge component.

Abstract: A method of making an interconnect substrate, comprising disposing an embedded component and at least one tracking identifier in a substrate core, and planarizing the substrate core to form a planar surface, forming a conductive layer over a frontside planar surface, disposing a layer of dielectric over the frontside planar surface, the embedded component, and the conductive layer, rotating the substrate core such that a back surface of the substrate core is configured for processing, and forming a conductive layer over the back surface of the substrate core.

Abstract: A method of making a semiconductor assembly may include mounting a plurality of components to a patterned element on an intermediate carrier, and disposing an encapsulant over the intermediate carrier, where the encapsulant may be disposed around four side surfaces of each of the plurality of components and one or more of the plurality of components may comprise conductive studs disposed over a front surface of the components. The method may further include removing a portion of the encapsulant to form a planar surface above the front surface, wherein the planar surface comprises ends of the conductive studs and a planar surface of the encapsulant. The method may further comprise removing the intermediate carrier through a grinding process, and terminating the grinding process when at least a portion of the patterned element is exposed.

Abstract: Disclosed is an interposer comprising a bridge having a component comprising a base material and one or more bridge redistribution layers (RDLs) disposed over the component, where the bridge RDLs comprise alternating layers of electrically conductive traces and interleaved dielectric layers comprising polyimide, and a bridge encapsulant disposed between the bridge RDLs, including through mold interconnects disposed in a periphery of the bridge, an encapsulant disposed around the through mold interconnects and around the bridge component, and a frontside interposer build-up over the encapsulants, over the through mold interconnects, and over the bridge.

Abstract: Disclosed is an assembly comprising a 3D block comprising a support material disposed around a conductive element, where the support material comprises a cut or ground edge and a portion of a wafer, the assembly further comprising at least one component disposed adjacent the 3D block, and an encapsulant disposed around the 3D block and around the at least one component, and a first interconnect structure formed over, and coupled with, first ends of the conductive elements, where the first ends are exposed with respect to the support material.

Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Abstract: A method of making an interconnect substrate, comprising disposing an embedded component and at least one tracking identifier in a substrate core, and planarizing the substrate core to form a planar surface, forming a conductive layer over a frontside planar surface, disposing a layer of dielectric over the frontside planar surface, the embedded component, and the conductive layer, rotating the substrate core such that a back surface of the substrate core is configured for processing, and forming a conductive layer over the back surface of the substrate core.

Abstract: The disclosure concerns methods of forming a semiconductor device with a repairable redistribution layer (RDL) design, comprising: preparing an original repairable RDL design; forming first conductive segments of the repairable RDL design; inspecting the first conductive segments of the repairable RDL design to detect manufacturing defects; detecting at least one defect in the first conductive segments; and forming second conductive segments of the repairable RDL design according to a new custom RDL design to mitigate the negative effects of the at least one defect among the first conductive segments. The disclosure also concerns semiconductor devices with a repairable RDL design.

Abstract: A method of making a semiconductor assembly may include mounting a plurality of components to one or more intermediate carriers and disposing the one or more intermediate carriers over a temporary carrier. The intermediate carriers may comprise one or more conductive features and coupling the components to the conductive features. The method may further include disposing an encapsulant over the one or more intermediate carriers and over the plurality of components mounted to the temporary carrier to form a reconstituted panel. The encapsulant may be disposed around four side surfaces and over a front surface of each of the plurality of components and removing a portion of the encapsulant to form a planar surface above the front surface of the plurality of components and removing the temporary carrier.

Abstract: A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

Abstract: A method of making a QFN, DEN, or SON package may comprise forming an embedded chip panel comprising a plurality of semiconductor chips embedded in encapsulant and separated by saw streets. A conductive layer may be formed over the embedded chip panel, the conductive layer comprising bussing lines, contact pads, traces, and tie bars, wherein the bussing lines and tie bars extend into the saw streets. Vertical conductive elements may be disposed over and coupled with the conductive layer. An encapsulant layer may be disposed over the conductive layer and around the vertical conductive elements, wherein the vertical conductive elements comprise exposed ends and at least a portion of the tie bars is exposed from the encapsulant layer. Land pads, a conductive pad finish, or SMS may be electroplated over the vertical conductive elements by providing a current through the bussing lines and tie bars.

Abstract: A substrate comprising a region of displacement compensation traces (DCTs), a component comprising conductive contacts, interconnect pads formed in an interconnect pad region over the component according to a nominal design position, first and second embedded components, and a region of DCTs comprising at least one arrangement of DCTs with unit specific patterning such that the arrangement of DCTs is coupled to, and extends between, the conductive contacts and the interconnect pads.

Abstract: A semiconductor device may comprise a bridge die comprising copper studs. Copper posts may be disposed in a periphery of the bridge die. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure comprising first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die. The first pitch may be at least 1.5 times less than the second pitch.

Abstract: A method of making an assembly or package comprising 3D blocks may include forming a conductive element horizontally oriented over a first carrier, forming support material around the conductive element, and singulating the conductive element and the support material to form a plurality of 3D blocks. The method may further include rotating each of the plurality of 3D blocks and mounting the plurality of 3D blocks over a second carrier with the conductive traces of the 3D blocks vertically oriented to form a vertically oriented conductive element. A plurality of components may be disposed laterally offset from each of the plurality of 3D blocks, an encapsulant may be disposed thereover s to form a reconstituted panel that may be singulated to form a plurality of individual assemblies.

Abstract: A semiconductor assembly comprising an intermediate carrier which is not an interposer and does not comprise electrical routing in or on the intermediate carrier, a plurality of components disposed over the intermediate carrier such that an active surface of the plurality of components is oriented away from the intermediate carrier, where the plurality of components have a thickness in a range of 2-500 micrometers (?m) and one or more components comprise conductive studs disposed over a front surface, an encapsulant contacting the intermediate carrier and the plurality of components, where the encapsulant contacts sides of the conductive studs, four side surfaces and the front surface of the plurality of components, and the encapsulant comprises a planar surface above the front surface of the plurality of components, and the planar surface comprises ends of the conductive studs and a planar surface of the encapsulant.

Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Abstract: A method of forming a semiconductor device can comprise providing a first shift region in which to determine a first displacement. A second shift region may be provided in which to determine a second displacement. A unique electrically conductive structure may be formed comprising traces to account for the first displacement and the second displacement. The electrically conductive structure may comprise traces comprising a first portion within the first shift region and a second portion of traces in the second shift region laterally offset from the first portion of traces. A third portion of the traces may be provided in the routing area between the first shift region and the second shift region. A unique variable metal fill may be formed within the fill area. The variable metal fill may be electrically isolated from the unique electrically conductive structure.

Abstract: A method of making a substrate comprising an embedded component and further comprising a region of displacement compensation traces (DCTs) may comprise the following. A component comprising conductive contacts. Measuring a shift of the component. Forming a plurality of interconnect pads over the component according to a nominal design position. Forming the region of DCTs may comprise at least one arrangement of DCTs with unit specific patterning such that the arrangement of DCTs is coupled to, and extends between, the conductive contacts and the interconnect pads. The arrangement of DCTs may compensate for the measured shift of the component and a majority of the arrangement of DCTs does not extend beyond a shared footprint of the component and the interconnect pad region.

Abstract: An electronic assembly component may comprise at least one fan-out device comprising a first encapsulant disposed around a memory device or function and a processor device or function, and a fan-out interconnect structure disposed over the first encapsulant and the at least one fan-out device. Input output pads may be disposed over the fan-out interconnect structure. A structural support may comprise electrical routing and structural support pads, the structural support further comprising at least one mounting site to which the at least one fan-out device is coupled. An electrical connector may be configured to electrically couple the input output pads of the at least one fan-out device to the structural support pads. A second encapsulant may be disposed over at least a portion of the at least one fan-out device and the structural support.