Abstract: Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors.

Abstract: Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data.

Abstract: Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors.

Abstract: Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors.

Abstract: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals.

Abstract: Methods and apparatus are disclosed, such as those involving mixed-mode signaling that includes transmitting a differential signal and a common mode signals over the same pair of interconnect traces. One such apparatus includes a first transmitter configured to transmit a differential signal through a pair of electrically conductive lines in a first direction. The differential signal has a first frequency and carries electronic data. The apparatus further includes a second transmitter configured to transmit a common mode signal through the pair of electrically conductive lines in the first direction. The common mode signal is superimposed onto each of the differential signal. The common mode signal has a second frequency that is lower than the first frequency and carries a control signal. This configuration reduces the number of lines and pins on electronic circuits, thereby saving space thereon.

Abstract: Semiconductor dies and methods are described, such as those including a first capacitive pathway having a first effective series resistance (ESR) and a second capacitive pathway having an adjustable ESR. One such device provides for optimizing the semiconductor die for different operating conditions such as operating frequency. As a result, semiconductor dies can be manufactured in a single configuration for several different operating frequencies, and each die can be tuned to reduce (e.g. minimize) supply noise, such as by varying the ESR or the capacitance of at least one of the pathways.

Abstract: Methods implementable in a computer system for simulating the transmission of signals are disclosed. The disclosed techniques simulate the effect of the transmitter as well as the channel on a positive and negative pulse, which assures that asymmetry in the transmitter is captured. The resulting positive and negative pulse responses are then used to generate two separate PDFs: one indicative of received logic ‘1’s and another indicative of received logic ‘0’s at a point in time. Generating a plurality of such PDFs at different times allows the reliability of data reception to be assessed, and appropriate sensing margins to be set at a receiver, without the need to simulate the transmission of a very long random stream of data bits.

Abstract: Apparatus and methods level shift a direct current (DC) component of a voltage rail signal from a first DC level to a second DC level such that voltage rail noise can be determined. The actual voltage rail noise can be compared to an expected amount of noise for analysis and validation of simulation models. Such assessment can be used to validate simulation models used to refine a design of an integrated circuit or as part of built-in self test.

Abstract: Methods and apparatus disclosed herein operate to receive a plurality of cycles characterized by a set of time-domain aspects, to modify at least one of the time-domain aspects of at least some of the plurality of cycles to produce a plurality of modified cycles, to process at least some of the modified cycles to produce time-domain cycles, and to create a time-domain signal based at least in part on concatenating the time-domain cycles.

Abstract: Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack.

Abstract: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals.

Abstract: Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises determining a maximum voltage margin and a maximum timing margin of a received signal, and from these margins, determining an optimal sampling point, which includes a reference voltage level (Vref) and a relative sample phase. The location of the optimal sampling point is based on the locations of the sampling point of the maximum voltage margin and the sampling point of the maximum timing margin. A second method comprises establishing an initial sampling point, and then successively refining each of the voltage and timing components of the sampling point until an optimal sampling point is reached.

Abstract: Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data.

Abstract: Apparatuses and methods for driving input data signals onto signal lines as output data signals are disclosed. An example apparatus includes a detection circuit, a driver adjust circuit, and a data driver. The detection circuit is configured to detect a characteristic(s) of a group of input data signals to be driven onto adjacent signal lines. A characteristic could be, for example, a particular combination of logic levels and/or transitions for the group of input data signals. The driver adjust circuit is configured to provide a driver adjustment signal based at least in part on a detection signal, that is provided by the detection circuit. A data driver is configured to drive a respective one of the group of input data signals as a respective one of the output data signals, wherein the data driver is adjusted based at least in part on the driver adjustment signal.

Abstract: Methods and apparatus disclosed herein operate to receive a plurality of cycles characterized by a set of time-domain aspects, to modify at least one of the time-domain aspects of at least some of the plurality of cycles to produce a plurality of modified cycles, to process at least some of the modified cycles to produce time-domain cycles, and to create a time-domain signal based at least in part on concatenating the time-domain cycles.

Abstract: An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset.

Abstract: In various embodiments, a reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (e.g., Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply.

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract: Computer-implementable recursive summation algorithms are disclosed that are useful for efficiently performing recursive convolution, such as is often required in Statistical Signal Analysis (SSA) techniques. The disclosed recursive summation algorithms can be more computationally-efficient from both a speed and memory perspective than other recursive convolution techniques known in the prior art, such as the techniques relying on Fast Fourier Transforms (FFTs).