Patents by Inventor Tin-Hao Kuo

Tin-Hao Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure and formation method of chip package with fan-out structure
    Patent number: 10163801
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive feature and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer arranged over the semiconductor die and the protection layer and partially covering the conductive feature. The conductive feature is arranged accessibly from the protection layer and the dielectric layer. The chip package further includes a conductive layer penetrating through the dielectric layer and electrically connected to the conductive feature of the semiconductor die. The conductive feature has a first portion covered by the dielectric layer and a second portion accessibly exposed from the dielectric layer, and the second portion has a surface roughness greater than that of the first portion.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo
  • Semiconductor device having conductive bumps of varying heights
    Patent number: 10163844
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a recess filled with a conductive material electrically coupled to at least one of the plurality of conductive traces. The semiconductor structure also includes semiconductor chip. The semiconductor chip includes a plurality of conductive pads correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Contact area design for solder bonding
    Patent number: 10157874
    Abstract: A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Chun Tsai, Yu-Feng Chen, Tin-Hao Kuo, Chen-Shien Chen, Yu-Chih Huang, Sheng-Yu Wu
  • Conical-Shaped or Tier-Shaped Pillar Connections
    Publication number: 20180358316
    Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
    Type: Application
    Filed: August 20, 2018
    Publication date: December 13, 2018
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang
  • Dual-sided integrated fan-out package
    Patent number: 10153249
    Abstract: A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein forming the RDL includes the steps of forming a seed layer, forming a first patterned mask over the seed layer, and performing a first metal plating. The method further includes forming through vias on top of a first portion of the RDL, wherein forming the through vias includes forming a second patterned mask over the seed layer and the RDL, and performing a second metal plating. The method further includes attaching a chip to a second portion of the RDL, and encapsulating the chip and the through vias in an encapsulating material.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Wei Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
    Patent number: 10153243
    Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. A method of forming a device includes forming a conductive trace over a first substrate, the conductive trace having first tapering sidewalls, forming a conductive bump over a second substrate, the conductive bump having second tapering sidewalls and a first surface distal the second substrate, and attaching the conductive bump to the conductive trace via a solder region. The solder region extends from the first surface of the conductive bump to the first substrate, and covers the first tapering sidewalls of the conductive trace. The second tapering sidewalls of the conductive bump are free of the solder region.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jen Tseng, Yen-Liang Lin, Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii
  • Method of Manufacturing an Integrated Fan-out Package having Fan-Out Redistribution Layer (RDL) to Accommodate Electrical Connectors
    Publication number: 20180342435
    Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.
    Type: Application
    Filed: August 2, 2018
    Publication date: November 29, 2018
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Hao-Yi Tsai, Tin-Hao Kuo
  • Integrated fan-out stacked package with fan-out redistribution layer (RDL)
    Patent number: 10128213
    Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Hao-Yi Tsai, Tin-Hao Kuo
  • Substrate design with balanced metal and solder resist density
    Patent number: 10128195
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Conical-shaped or tier-shaped pillar connections
    Patent number: 10056345
    Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang
  • CHIP PACKAGE WITH FAN-OUT STRUCTURE
    Publication number: 20180233382
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 16, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shing-Chao CHEN, Chih-Wei LIN, Meng-Tse CHEN, Hui-Min HUANG, Ming-Da CHENG, Kuo-Lung PAN, Wei-Sen CHANG, Tin-Hao KUO, Hao-Yi TSAI
  • Bump-on-trace structures with high assembly yield
    Patent number: 10050000
    Abstract: A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 ?m2 and about 1,300 ?m2.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Fan Huang, Chen-Shien Chen, Chung-Shi Liu, Ming-Da Cheng, Tin-Hao Kuo, Yi-Teh Chou
  • Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
    Patent number: 10049953
    Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Hao-Yi Tsai, Tin-Hao Kuo
  • Integrated circuit packaging substrate, semiconductor package, and manufacturing method
    Patent number: 10043774
    Abstract: An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body. The second conductive line is embedded in the main body. The protrusion pad is disposed on the first conductive line. The protrusion pad protrudes from the main body and is configured to be in electrical contact with a solder portion of a semiconductor chip. A first spacing between the protrusion pad and the second conductive line is determined in accordance with a process deviation of the protrusion pad by the width of the protrusion pad and the width of the first conductive line. Moreover, a semiconductor package having the IC packaging substrate and a manufacturing method of the semiconductor package are also provided.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wei Lin, Chen-Shien Chen, Guan-Yu Chen, Tin-Hao Kuo, Yen-Liang Lin
  • SEMICONDUCTOR STRUCTURE WITH CONDUCTIVE STRUCTURE
    Publication number: 20180218953
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed over the substrate. The semiconductor device structure also includes a protection layer formed over the conductive pad, and the protection layer has a trench. The semiconductor device structure further includes a conductive structure accessibly arranged through the trench of the protection layer and electrically connected to the conductive pad. The conductive structure has a curved top surface that defines an apex, and an apex of the curved top surface is higher than a top surface of the protection layer.
    Type: Application
    Filed: March 28, 2018
    Publication date: August 2, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Chun TSAI, Wei-Sen CHANG, Tin-Hao KUO, Hao-Yi TSAI
  • Integrated Fan-out Package and the Methods of Manufacturing
    Publication number: 20180197837
    Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Hao-Yi Tsai, Tin-Hao Kuo
  • Protrusion bump pads for bond-on-trace processing
    Patent number: 10020276
    Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Shien Chen, Yu-Feng Chen, Yu-Wei Lin, Tin-Hao Kuo, Yu-Min Liang, Chun-Hung Lin
  • Structures having a tapering curved profile and methods of making same
    Patent number: 10008459
    Abstract: An embodiment ladder bump structure includes an under bump metallurgy (UBM) feature supported by a substrate, a copper pillar mounted on the UBM feature, the copper pillar having a tapering curved profile, which has a larger bottom critical dimension (CD) than a top critical dimension (CD) in an embodiment, a metal cap mounted on the copper pillar, and a solder feature mounted on the metal cap.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Pei-Chun Tsai, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Bump structure and method of forming same
    Patent number: 9966346
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Guan-Yu Chen, Yu-Wei Lin, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Conductive contacts having varying widths and method of manufacturing same
    Patent number: 9953939
    Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen