Patents by Inventor Ting AN

Ting AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240159752
    Abstract: Disclosed herein is a method for determining whether a subject has or is at risk of developing colorectal cancer with an ex vivo biological sample isolated from the subject. The method comprises: determining the levels of at least two target proteins with the aid of mass spectrometry, in which the at least two target proteins are selected from the group consisting of ADAM10, CD59, and TSPAN9; and assessing whether the subject has or is at risk of developing the colorectal cancer based on the levels of the at least two target proteins. The present method may serve as a potential means for diagnosing and predicting the incidence of colorectal cancer, and the subject in need thereof could receive a suitable therapeutic regimen in time in accordance with the diagnostic results produced by the present method.
    Type: Application
    Filed: February 20, 2023
    Publication date: May 16, 2024
    Applicant: Chang Gung University
    Inventors: Jau-Song YU, Srinivas DASH, Chia-Chun WU, Sheng-Fu CHIANG, Yu-Ting LU
  • Publication number: 20240157496
    Abstract: A method for facilitating analysis of causes of machining defects is provided. The method is carried out by a computer system. The method includes the step of obtaining motion data and vibration acceleration data about the tip of a cutter mounted on a machine tool. The method further includes the step of obtaining time-frequency information about the vibration acceleration data by performing a time-frequency analysis on the vibration acceleration data. The method further includes the step of obtaining vibration-displacement data by normalizing the time-frequency information. The method further includes the step of obtaining amplitude-distribution data about the tip by synchronizing the motion data and the vibration-displacement data.
    Type: Application
    Filed: December 19, 2022
    Publication date: May 16, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Ting CHEN, Jheng-Jie LIN, Chien-Chih LIAO, Jen-Ji WANG
  • Publication number: 20240160741
    Abstract: A data processing system in an off-line status includes a BIOS device and at least one processor. The BIOS device is for calculating a current system time. The at least one processor executes an operating system. The operating system includes a time logging driver resident in a driver layer of the operating system and an application layer start/end time recording process resident in an application layer of the operating system. The time logging driver records a driver start time and a driver end time. The application layer start/end time recording process records an application layer start time and an application layer end time. The data processing system of the invention, according to the application layer start time, the application layer end time, the driver start time and the driver end time, adjusts the current system time to prevent the current system time from being tampered.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 16, 2024
    Inventor: Ting-Huang CHEN
  • Publication number: 20240158957
    Abstract: The present invention provides a polyurethane nanofiber waterproof moisture-permeable film, a preparation method thereof and application thereof. The polyurethane nanofiber waterproof moisture-permeable film is prepared from two kinds of isothiocyanate and two kinds of polyethylene glycol as raw materials, and the polyurethane nanofiber waterproof moisture-permeable film has good water pressure resistance, tensile property, and moisture permeability. In addition, the polyurethane nanofiber waterproof moisture-permeable film is prepared by adopting an electrostatic spinning method, is low in cost, simple to operate and high in production efficiency, and has a good application prospect in the fields of clothing, medical treatment, electronic appliances, and the like.
    Type: Application
    Filed: December 10, 2023
    Publication date: May 16, 2024
    Inventors: Xinglei ZHAO, Yong JIN, Pan JIANG, Ting HUA, Peng WANG
  • Publication number: 20240158943
    Abstract: The present disclosure is drawn to covers for electronic devices. In one example, a substrate can include a metal alloy. An acid anodizing layer can be formed on the substrate. A dye application can be applied on the acid anodizing layer. A first nickel-free sealing layer can be formed on the dye application. An alkaline anodizing layer can be formed on the first sealing layer. A second nickel-free sealing layer can be formed on the alkaline anodizing layer.
    Type: Application
    Filed: March 19, 2021
    Publication date: May 16, 2024
    Inventors: Qingyong GUO, Ya-Ting YEH, Chi Hao CHANG, Kuan-Ting WU
  • Publication number: 20240160815
    Abstract: Embodiments of the present disclosure provide a method, system, and storage medium for predicting an area of oil spill on sea surface, the method for predicting the area of oil spill on sea surface includes: S1, obtaining a training dataset; S2, constructing an oil spill numerical model, and determining a predictive model by performing a predetermined processing on an initial predictive model based on simulation result data and the training dataset; S3, initializing the predictive model, determining a count of nodes of an input layer, an output layer, and a hidden layer; and S4, obtaining input data and inputting the input data into the predictive model in S2 to obtain an oil spill area on sea surface to be measured. The method, when used, has a small error and high accuracy, can save a lot of material and financial resources, and can be more widely used in real life.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Applicant: CHANGZHOU UNIVERSITY
    Inventors: Hong JI, Ting WANG, Ke YANG, Yaxin WANG, Jie GUO
  • Publication number: 20240161176
    Abstract: Disclosed techniques enable cluster-based dynamic content with multi-dimensional vectors for video content analysis. User-specific data vectors on a plurality of users are accessed, which include shopping history and video consumption behavior. A plurality of clusters, based on the user-specific data vectors, is developed. A user, from the plurality of users, is associated with one or more clusters from the plurality of clusters. The user is identified as viewing media content. A container unit is inserted into the media content that is being viewed and is populated with at least one short-form video from a library of short-form videos. The populating is based on the identifying. An ecommerce purchase of a product for sale to the user is enabled. The product for sale is relevant to the one or more clusters and the at least one short-form video. The ecommerce purchase is accomplished within a short-form video window.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Applicant: Loop Now Technologies, Inc.
    Inventors: Edwin Chiu, Vishal Arora, Shi Feng, Jerry Ting Kwan Luk, Ziming Zhuang
  • Publication number: 20240162083
    Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chen-Han WANG, Keng-Chu LIN, Tetsuji UENO, Ting-Ting CHEN
  • Publication number: 20240162119
    Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein, the metallization patterns including a top metal layer including top metal structures, forming a passivation layer over the top metal structures of the first interconnect structure, forming a first opening through the passivation layer, forming a probe pad in the first opening and over the passivation layer, the probe pad being electrically connected to the first top metal structure, performing a circuit probe test on the probe pad, removing the probe pad, and forming a bond pad and a bond via in dielectric layers over the passivation layer, the bond pad and bond via being electrically coupled to a second top metal structure of the top metal structures and a third top metal structure of the top metal structures.
    Type: Application
    Filed: January 6, 2023
    Publication date: May 16, 2024
    Inventors: Ching-Yu Huang, Ting-Chu Ko, Der-Chyang Yeh
  • Publication number: 20240161672
    Abstract: An electronic circuit including a plurality of common terminals, a first circuit, a second circuit, and a plurality of switch units is provided. The first circuit is configured to output display driving signals to data lines of a display panel via the common terminals. The second circuit is configured to receive fingerprint sensing signals from fingerprint sensing lines of the display panel via the common terminals. Each of the switch units includes a first terminal coupled to one of the common terminals and a plurality of second terminals coupled to the first circuit and the second circuit. The switch units are grouped into a plurality of groups, and each group corresponds to a fingerprint sensing channel of the second circuit.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Huan-Teng Cheng, Ting-Hsuan Hung, Tzu-Wen Hsieh, Wei-Lun Shih, Huang-Chin Tang
  • Publication number: 20240162088
    Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsia-Wei CHEN, Fu-Ting SUNG, Yu-Wen LIAO, Wen-Ting CHU, Fa-Shen JIANG, Tzu-Hsuan YEH
  • Publication number: 20240162007
    Abstract: Embodiments of the present disclosure generally relate to a system used in a semiconductor device manufacturing process. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of an RF bias signal and a pulsed voltage waveform to one or more electrodes within a plasma processing chamber. The apparatus and methods disclosed herein can be useful to at least minimize or eliminate a microloading effect created while processing small dimension features that have differing densities across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve the control of various characteristics of the generated plasma and control an ion energy distribution (IED) of the plasma generated ions that interact with a surface of a substrate during plasma processing.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 16, 2024
    Inventors: Deyang LI, Sunil SRINIVASAN, Yi-Chuan CHOU, Shahid RAUF, Kuan-Ting LIU, Jason A. KENNEY, Chung LIU, Olivier P. JOUBERT, Shreeram Jyoti DASH, Aaron EPPLER, Michael Thomas NICHOLS
  • Publication number: 20240162318
    Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Inventors: Min-Kun DAI, Wei-Gang CHIU, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN
  • Publication number: 20240162084
    Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yen HUANG, Ting-Ya LO, Shao-Kuan LEE, Chi-Lin TENG, Cheng-Chin LEE, Shau-Lin SHUE, Hsiao-Kang CHANG
  • Publication number: 20240162159
    Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang WANG, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
  • Publication number: 20240162150
    Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, wherein each gate strip is arranged to be a gate terminal of a transistor; forming a plurality of first metal strips above the plurality of gate strips; and forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed from top view; wherein a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Inventors: SHIH-WEI PENG, HUI-TING YANG, WEI-CHENG LIN, JIANN-TYNG TZENG
  • Publication number: 20240161347
    Abstract: In implementations of image-based searches for templates, a computing device implements a search system to generate an embedding vector that represents an input digital image using a machine learning model. The search system identifies templates that include a candidate digital image to be replaced by the input digital image based on distances between embedding vector representations of the templates and the embedding vector that represents the input digital image. A template of the templates is determined based on a distance between an embedding vector representation of the candidate digital image included in the template and the embedding vector that represents the input digital image. The search system generates an output digital image for display in a user interface that depicts the template with the candidate digital image replaced by the input digital image.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Applicant: Adobe Inc.
    Inventors: Brian Eriksson, Wei-ting Hsu, Santiago Pombo, Sandilya Bhamidipati, Rida Khan, Ravali Devarapalli, Maya Christmas Davis, Lam Wing Chan, Konstantin Blank, Jason Omid Kafil, Di Ni
  • Publication number: 20240161293
    Abstract: A multi-label classification method for generating labels annotated on medical images. An initial dataset including medical images and partial input labels is obtained. The partial input labels annotate a labeled part of abnormal features on the medical images. A first multi-label classification model is trained with the initial dataset. Difficulty levels of the medical images in the initial dataset are estimated based on predictions generated by the first multi-label classification model. The initial dataset is divided based on the difficulty levels of the medical images into different subsets. A second multi-label classification model is trained based on subsets with gradually increasing difficulty levels during different curriculum learning rounds. Predicted labels annotated on the medical images are generated about each of the abnormal features based on the second multi-label classification model.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 16, 2024
    Inventors: Zhe-Ting LIAO, Yu-Shao PENG
  • Publication number: 20240162401
    Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.
    Type: Application
    Filed: December 9, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chun-Ting Yeh
  • Publication number: 20240162164
    Abstract: A chip package with a metal shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), and a metal shielding layer. The chip is composed of a first surface and a second surface and cut from a wafer. The RDL is disposed on a surface of at least one chip protective layer of the chip and provided with at least one conductive circuit for electrical connection with the die pad of the chip. The conductive circuit includes at least one pad which is exposed on a surface of the RDL for electrical connection with the outside. The metal shielding layer is covering the second surface of the chip not only for protecting the chip and the conductive circuit from external electromagnetic interference or light interference but also for increasing structural strength of the chip package.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU