Abstract: A deep learning fault diagnosis method includes the following steps: a fault diagnosis data set X is processed based on sliding window processing, to obtain a picture-like sample data set {tilde over (X)}, and obtain an attention matrix A of the picture-like sample data set {tilde over (X)}; and a 2D-CNN model is constructed to process the picture-like sample data set {tilde over (X)} to obtain a corresponding feature map F, and in the meantime, the feature map F is processed based on channel-oriented average pooling and channel-oriented maximum pooling to obtain an output P1 of the average pooling and an output P2 of the maximum pooling, and a weight matrix W is obtained based on the attention matrix A, the output P1 of the average pooling, and the output P2 of the maximum pooling, so that an output of the model is a feature map {tilde over (F)} based on an attention mechanism, where {tilde over (F)}=WF.

Abstract: In a wire drawing method, processing stability is ensured by preventing a shape from deforming non-uniformly. The wire drawing method includes: using a first wire that includes a center member, a plurality of first peripheral wires surrounding the center member, and an outer shell disposed outside the first peripheral wires; and reducing a cross-sectional diameter of the first wire by wire drawing. A shape of a cross section perpendicular to a longitudinal direction of the first peripheral wire is a substantially isosceles trapezoidal shape including a long side in contact with the outer shell, a short side in contact with the center member, and a first oblique side and a second oblique side that are in contact with the adjacent peripheral wires.

Abstract: Some embodiments of the present disclosure relate to an integrated chip, including a semiconductor substrate and a dielectric layer disposed over the semiconductor substrate. A pair of metal lines are disposed over the dielectric layer and laterally spaced apart from one another by a cavity. A barrier layer structure extends along nearest neighboring sidewalls of the pair of metal lines such that the cavity is defined by inner sidewalls of the barrier layer structure and a top surface of the dielectric layer.

Abstract: The compositions of the present disclosure polish surfaces or substrates that at least partially include ruthenium. The composition includes a synergistic combination of ammonia and oxygenated halogen compound. The composition may further include abrasive and acid(s). A polishing composition for use on ruthenium materials may include ammonia, present in an amount of 0.01 wt % to 10 wt %, based on the total weight of the composition; hydrogen periodate, present in an amount of 0.01 wt % to 10 wt %, based on the total weight of the composition; silica, present in an amount of 0.01 wt % to 12 wt %, based on the total weight of the composition; and organic sulfonic acid, present in an amount of 0.01 wt % to 10 wt %, based on the total weight of the composition, wherein the pH of the composition is between 6 and 8.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: A ceiling fan blade assembly structure includes a blade holder, multiple fan blades, and multiple locking assemblies. Multiple fan blade assembly portions are disposed at an outer side of the blade holder. Each fan blade assembly portion includes two first side plates parallel to each other, a first radial positioning portion, and two first vertical positioning portions disposed on the two first side plates. Each fan blade has a fan blade connection portion that includes two second side plates, a second radial positioning portion, and two second vertical positioning portions. The second and the first radial positioning portions are engaged with each other, and the two second and first vertical positioning portions are engaged with each other. Accordingly, the fan blade connection portion is preliminarily positioned on the fan blade assembly portion. Through the locking assembly, the first and the second radial positioning portions are locked together.

Abstract: A display control method applicable to an all-in-one (AIO) computer is provided. The AIO computer includes a first monitor and a second monitor. The display control method includes: receiving a control instruction from the first monitor; projecting a display content on the second monitor according to the control instruction; and selectively enabling a touch control function of the second monitor according to the control instruction.

Abstract: In one aspect, a sensor includes a first metal layer portion and a second metal layer portion separated by an insulator material; a conductive material layer in electrical contact with the first metal layer portion and the second metal layer portion; and a tunnel magnetoresistance (TMR) element positioned on and in electrical contact with the conductive material layer. A first current is configured to flow from the first metal layer portion, through the conductive material layer, to the second metal layer portion, and a second current is configured to flow from the first metal layer portion, through the conductive material layer, through the TMR element, and exiting through a top of the TMR element.

Abstract: The present disclosure provides an immunoconjugate includes an antibody comprising an antigen-binding fragment that specifically binds to an epitope in mesothelin, N-glycan binding domain and an N-glycan; a linker linking to the N-glycan; and a payload A and a payload B conjugated to the linker, respectively; wherein the payload A and the payload B are the same or different. A pharmaceutical composition comprises the immunoconjugate and a method for treating cancer are also provided in the disclosure.

Abstract: An immersion cooling tank includes a tank body and a liquid flow tube. The tank body holds a coolant and an electronic device. The tank body defines an inlet and an outlet. The inlet and the outlet are respectively located at opposite ends of the electronic device for inputting and outputting the coolant. The coolant flows through the electronic device. The liquid flow tube includes at least one adjuster. The liquid flow tube is located inside the tank body and coupled to at least one of the inlet or the outlet. The at least one adjuster faces the electronic device for controlling an amount of the coolant flowing in or out of the tank body.

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

Abstract: A gamma correction method and apparatus, electronic device and readable storage medium.

Abstract: The disclosure provides an electronic device adapted to communicate with a stylus. The electronic device includes a display panel, a touch module, and a processor. The display panel has a display area, the touch module has a touchable area, and the processor is electrically connected to the display panel and the touch module. The processor is configured to: define at least one effective input area in response to an operation of the stylus in the touchable area, and when the touch module detects that the stylus is approaching the effective input area, switch the effective input area to a stylus mode, and display a range marking pattern in the effective input area.

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

Abstract: A multi-band network node has selectable backhaul/fronthaul configurations. Network nodes provide multi-band operation to take advantage of higher Internet speeds and to support lower latency (>2 Gbps, <4 ms latency) applications. A greater Wi-Fi device count (capacity) is supported by implementing communication over additional bands. Increased bandwidth is made available between connected nodes by selectively combining backhaul throughputs. Hardware quality-of-service (QoS) is provided by splitting traffic flows for low latency and data applications. Network coverage is extended by dynamic assignment of backhaul connections and by configuring unused backhauls as fronthauls.

Abstract: A method includes forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; etching the dummy gate material using a first etching process to form a recess between the first fin and the second fin, wherein a sacrificial material is formed on sidewalls of the recess during the first etching process; filling the recess with an insulation material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate over the first fin and a second replacement gate over the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulation material.

Abstract: The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.