Abstract: Semiconductor structures and processes for forming the same provided. A semiconductor structure according to the present disclosure includes an insolation feature, a first base fin and a second base fin extending through and rising above the isolation feature, a first active region disposed over the first base fin, a second active region disposed over the second base fin, a gate structure disposed over the first active region, the second active region, and the isolation feature, and a protection layer sandwiched between the gate structure and the isolation feature.

Abstract: The present disclosure provides polypeptide conjugates comprising GLP-1 receptor agonist and a peptide linker, and liquid pharmaceutical compositions comprising the same. Methods of using such for treating diseases are also provided.

Abstract: An intrusion detection and prevention system (IDPS) has detection probes and detection hubs that are deployed onboard a connected vehicle and a detection correlation backend that is deployed on the cloud. A detection probe receives raw packets of network traffic of a communication network of the connected vehicle. The detection probe filters the raw packets in accordance with packet filter rule entries to generate packets of interest. The detection probe scans the packets of interest for data indicative of network threats and outputs corresponding unfiltered detection logs. The detection probe filters the unfiltered detection logs in accordance with detection filter rule entries to generate detection logs of interest. A detection hub aggregates detection logs of interest from one or more detection probes to generate aggregated detection logs. A detection correlation backend evaluates the aggregated detection logs to detect network threats.

Abstract: The invention belongs to the field of biomedicine technology and discloses the application of Gastrodia elata Blume derived nano-extracellular vesicles in the preparation of drugs for the prevention and/or treatment of subarachnoid hemorrhage (SAH). The Gastrodia elata Blume-derived nano-extracellular vesicles of this invention are obtained from separation of Gastrodia elata Blume by water extraction. The ingredients of this invention are natural, none of toxic side effects and with good biocompatibility and safety. Therefore, this invention has broad application prospects.

Abstract: A method for forming a chip package structure is provided. The method includes providing an electrical substrate and a photonic substrate over and bonded to the electrical substrate. The method includes partially removing the dielectric structure to form a first through hole and a second through hole in the dielectric structure. The first through hole passes through the dielectric structure and exposes the first wiring layer. The method includes forming a first conductive via structure and a second conductive via structure in the first through hole and the second through hole respectively. The first conductive via structure is in direct contact with the first wiring layer, and the second conductive via structure is spaced apart from the first wiring layer.

Abstract: A semiconductor device includes a substrate, an outer detection wire and an inner detection wire. The substrate has a periphery lateral surface. The outer detection wire is disposed on the substrate and adjacent to the periphery lateral surface. The inner detection wire is disposed on the substrate, adjacent to the periphery lateral surface, and isolated from the outer detection wire. The outer detection wire is closer to the periphery lateral surface than the inner detection wire.

Abstract: A heat dispensing structure for an electric device includes an electric element, a heat dissipating unit opposite to the electric element along a first direction and an elastic heat dissipating structure located between the electric element and the heat dissipating unit along the first direction. The elastic heat dissipating structure includes a first elastic arm having a first fixed end and a first movable end and a second elastic arm having a second fixed end and a second movable end. The first and second fixed ends are fixedly connected to one of the electric element and the heat dissipating unit, and the first and second movable ends contact another one of the two. The first movable end and the second movable end are separated by a first distance before being pressed and by a second distance after being pressed, and the second distance is larger than the first distance.

Abstract: An electronic device is provided. The electronic device includes a plurality of processing units constituting a processing array having a first area, a surface supporting the processing array, and an optical channel. The surface has a second area, and the first area is greater than 80 percent of the second area. The optical channel is configured to transmit a first signal between at least two of the plurality of processing units in a first direction that is nonparallel with a normal direction of the surface.

Abstract: An electronic device is provided. The electronic device includes a plurality of electronic components and a circuit structure connected to the plurality of electronic components. The circuit structure is configured to connect the electronic components adjacent to each other along a first path, and the circuit structure is further configured to connect the electronic components that are not adjacent to each other along a second path having a greater length and a higher speed than the first path.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A horizontally polarized omnidirectional multi-band antenna structure includes a substrate and two structurally-symmetric radiators, each being provided on a layout area on one of the two opposite sides of the substrate, and including a X-shaped primary microstrip line, four secondary microstrip lines, four primary stubs, four secondary stubs and four resonators. The primary microstrip line has four end points arranged with the secondary microstrip lines along different extending directions. The primary stubs extend along different directions from four sections of the primary microstrip line. Each secondary microstrip line is provided with one of the secondary stubs. Resonators are provided between four end points of the primary microstrip line and the primary stubs.

Abstract: A method of protecting a device (protected device) (in a semiconductor system from an electrostatic discharge (ESD)) includes: coupling the protected device between a first node and a first reference voltage; coupling an ESD device between the first node and the first reference voltage; and selectively and actively coupling an input of the ESD device to a second reference voltage thereby selectively and actively turning on the ESD device.

Abstract: Provided is a sequential-pulse single-frequency laser power amplification apparatus, which comprises a sequence control unit for modulating and switching a source laser to output a primary laser, and a power amplification unit for amplifying the primary laser to output a secondary laser. Also provided is a sequence controllable multi-laser system comprising a plurality of single-frequency and/or multi-frequency laser power amplification apparatuses. This allows a single ultra-narrow linewidth laser device to meet the experimental requirements of multiple platforms in an atomic experiment, achieving high performance at low costs.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.

Abstract: A backlight control circuit includes a power supply circuit, a local dimming circuit, a backlight driving circuit, and a supply voltage adjustment circuit. The power supply circuit is used to output the power supply voltage to a backlight module. The backlight module has multiple dimming zones, and each dimming zone has light emitting diodes (LEDs). The local dimming circuit is used to generate a local dimming signal according to image data and a configuration of the dimming zones. The backlight driving circuit is used to generate backlight driving signals to the dimming zones of the backlight module according to the local dimming signal. The supply voltage adjustment circuit is used to generate a first supply voltage adjustment signal to the power supply circuit for adjusting the power supply voltage based on the local dimming signal and a characteristic data of each LED in the dimming zones.

Abstract: A data mining-based method for real-time production quality prediction of aluminum alloy casting, includes: (1) based on mold flow analysis results, installing sensors on a casting mold; wherein the sensors include at least one temperature sensor, at least one pressure sensor, at least one contact sensor, and a multi-functional gas sensor; (2) during casting production, real-time collecting temperatures, pressures, and contact times of the aluminum liquid at a plurality of locations of the casting mold, and pressure, composition, humidity, and temperature of gas in a mold cavity, by the installed sensors, for constructing an aluminum alloy casting process parameter set; and (3) inputting the process parameter set to a production quality prediction model; wherein the production quality prediction model is used to judge whether the production quality is qualified, which is obtained by mining a relationship between history casting process parameters and casting quality data.

Abstract: A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.

Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.

Abstract: A method for performing block level exploration of integrated circuit (IC) design and associated electronic device and computer-readable medium are provided. The method may include running a synthesis control procedure on at least one processor within the electronic device, for performing automatic placement and routing of a target design of an IC.

Abstract: A strength prediction method for laser bonded composite materials includes the following steps: establishing an initial geometric model that includes an initial solid geometric model and an initial surface geometric model in contact with each other; receiving metal material information, non-metal material information and layer formation parameters; setting material property parameters of the initial solid geometric model according to the metal material information to generate a solid model; generating a layer model according to the non-metal material information and a layer thickness and a layer quantity that are included in the layer formation parameters; setting material property parameters of the initial surface geometric model according to the layer model to generate a surface model; setting connection between the solid model and the surface model as laser bonding to generate a composite structural model; and performing a tensile test simulation to the composite structural model to obtain a simulation res