Abstract: The present disclosure discloses a servo motor and an encoder calibration method. The encoder calibration method includes: calculating a gain error, an offset error and a phase error, by an error calculation block, according to a first signal and a second signal output by an encoder; calculating at least one gain calibration parameter, at least one offset calibration parameter and at least one phase calibration parameter, by the error calibration block, according to the gain error, the offset error and the phase error; and calibrating sequentially, by the encoder, the gain, the offset and the phase of the first signal and the second signal according to the at least one gain calibration parameter, the at least one offset calibration parameter and the at least one phase calibration parameter, wherein performing at least one gain calibration and offset calibration after the phase calibration is completed.

Abstract: The present disclosure provides methods, drug combinations and kits for treating, ameliorating, reversing and/or preventing a Helicobacter pylori (H. pylori) infection in a patient in need thereof.

Abstract: An exercise intensity assessing system includes a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser exercises. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database for being diagnosed and analyzed by a fitness instructor. The cloud database obtains a forecasted watt value corresponding to the physiological information, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.

Abstract: An intelligent exercise intensity assessing system includes an exercise testing machine, a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser operates the exercise testing machine. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database. The cloud database analyzes the physiological information to obtain a corresponding forecasted watt value, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.

Abstract: A static auto-tuning system and method for controlling operation of a motor in a system. A speed reference signal is generated resulting in a speed response of the motor. Closed-loop feedback magnifies the rotating friction effect to an observable level. Inertia and rotating friction coefficient values of the system are estimated based on the speed frequency response and a virtual damping coefficient. A fixed low frequency speed signal may result in a first frequency response function for determining virtual damping, and a variable frequency excitation signal may result in a second frequency response function for determining the inertia and rotating friction characteristics. Closed-loop gains are determined based on these characteristics. The excitation signal may be sampled and a peak value in each interval may be identified and stored to produce an envelope of peak values for determining the gain response. Operation of the motor is controlled using the determined gains.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: A semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. The substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. The dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.

Abstract: A method of forming a semiconductor device is provided. A transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. A first metal via is formed through the first dielectric layer and aside the transistor. A first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. The substrate is thinned from a second side of the substrate. A capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. A second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.

Abstract: A gate structure includes a metal layer, a barrier layer, and a work function layer. The barrier layer covers a bottom surface and sidewalls of the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. The work function layer surrounds the barrier layer.

Abstract: An edge exposure tool may include a lens adjustment device that is capable of automatically adjusting various parameters of an edge exposure lens to account for changes in operating parameters of the edge exposure tool. In some implementations, the edge exposure tool may also include a controller that is capable of determining edge adjustment parameters for the edge exposure lens and exposure control parameters for the edge exposure tool using techniques such as big data mining, machine learning, and neural network processing. The lens adjustment device and the controller are capable of reducing and/or preventing the performance of the edge exposure tool from drifting out of tolerance, which may maintain the operation performance of the edge exposure tool and reduce the likelihood of wafer scratching, and may reduce the down-time of the edge exposure tool that would otherwise be caused by cleaning and calibration of the edge exposure lens.

Abstract: An optical fiber network device includes a fiber and a photonic integrated circuit. Fiber receives a first optical signal and transmits a second optical signal. A first wavelength of first optical signal is different from a second wavelength of second optical signal. Photonic integrated circuit includes a laser chip, a photodetector, a wavelength division multiplexing coupler, a first optical modulation element and a second optical modulation element. Laser chip is disposed on photonic integrated circuit, and is configured to generate first optical signal. Photodetector detects second optical signal. Wavelength division multiplexing coupler is configured to couple first optical signal to fiber, and receives second optical signal. First optical modulation element is coupled to wavelength division multiplexing coupler and laser chip, and is configured to modulate first optical signal.

Abstract: An optical fiber transmission device includes a substrate, a photonic integrated circuit, and an optical fiber assembly. The photonic integrated circuit is disposed on an area of the substrate. The substrate has a protruding structure at an interface with an edge of the photonic integrated circuit. The optical fiber assembly includes an optical fiber and a ferrule that sleeves the optical fiber. The protruding structure of the substrate is configured to abut against the ferrule to limit the position of the optical fiber assembly in a vertical direction of the substrate, such that the protruding structure is a stopper for the optical fiber assembly in the vertical direction.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method includes forming a first conductive pad and a mask layer over the interconnect structure. The mask layer covers a top surface of the first conductive pad. The method includes forming a metal oxide layer over a sidewall of the first conductive pad. The method includes forming a second conductive pad over the first conductive pad and passing through the mask layer. The first conductive pad and the second conductive pad are made of different materials.

Abstract: Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A USB active optical cable and a plug capable of managing power consumption and state. The USB active optical cable and plug respectively comprises a first plug, a second plug, and an optical transmission medium used to connect the first plug and the second plug; the first plug and the second plug are configured to operate different operating states, including an initialization mode, a transmission mode, and a power saving mode, and they can switch between the different operating states. The USB active optical cable and plug are both based on the separate control of the transmitting unit and the receiving unit to distinguish different operating modes, provide necessary operating requirements and mode switching conditions for each mode, and also enable the checking and transmission of the plugging state in the power saving mode, thus facilitate the power consumption management of the active optical cable.

Abstract: A method includes forming a pad layer. The pad layer includes a first portion over a first part of a semiconductor substrate, and a second portion over a second part of the semiconductor substrate. The first portion has a first thickness, and the second portion has a second thickness smaller than the first thickness. The semiconductor substrate is then annealed to form a first oxide layer over the first part of the semiconductor substrate, and a second oxide layer over the second part of the semiconductor substrate. The pad layer, the first oxide layer, and the second oxide layer are removed. A semiconductor layer is epitaxially grown over and contacting the first part and the second part of the semiconductor substrate.

Abstract: A semiconductor structure includes a barrier layer over a channel layer, and a doped layer over the barrier layer. A gate electrode is over the doped layer and a doped interface layer is formed between the barrier layer and the doped layer. The doped interface layer includes a dopant and a metal. The metal has a metal concentration that follows a gradient function from a highest metal concentration to a lowest metal concentration.

Abstract: The present invention provides a transparent conductive substrate, sequentially comprising: a first resist layer, a first transparent conductive layer, a transparent core, a second transparent conductive layer, and a second resist layer; wherein the first resist layer is composed of a UV-light sensitive composition (C1); and the second resist layer is composed of a visible-light sensitive composition (C2). The present invention provides a double-side photolithographic method for manufacturing transparent conductive laminates. The transparent conductive laminates manufactured by the inventive method may be incorporated into touch panels.

Abstract: A memory device is provided, including an array of bit cells and a set of tracking cells. The set of tracking cells is arranged adjacent to the array of bit cells along a first direction. The set of tracking cells includes a set of first tracking cells configured to perform a read tracking operation and a set of second tracking cells configured to perform a write tracking operation and arranged adjacent to the set of first tracking cells along a second direction. First tracking cells in the set of first tracking cells are coupled in series with each other and arranged along the second direction, and second tracking cells in the set of second tracking cells are coupled in series with each other and arranged along the second direction.