Abstract: An active eye open monitor calibration apparatus and method for active eye open monitor calibration are provided. A reference clock signal and an eye open monitor clock signal are received and a calibration selecting signal is used to control whether the reference clock signal samples the eye open monitor clock signal. An indicator signal is output and received by a phase indicating determination circuit for performing a calibration flow and accordingly calculating a phase offset signal. The eye open monitor clock is corrected based on the phase offset signal, such that a calibrated eye open monitor clock signal is synchronously in phase with the reference clock signal. By employing the proposed eye open monitor calibration apparatus and method thereof, the invention is effective in achieving phase synchronization for an eye open monitor clock signal in related to its reference clock signal, solving the phase mismatch in the related arts.

Abstract: A method of fabricating a resistive random-access memory (RRAM) structure includes forming a first patterned metallization layer; disposing a dielectric layer on the first patterned metallization layer; and etching openings exposing first contact portions of the first patterned metallization layer, each opening having an annular tapered sidewall tapering inward to a corresponding one of the first contact portions.

Abstract: A memory structure includes a substrate, a barrier layer, an etch stop layer, a bottom electrode, a data storage feature and a top electrode. The substrate has a metal trench. The barrier layer is disposed over the metal trench. The etch stop layer surrounds the barrier layer, and, together with the barrier layer, completely covers the metal trench. The bottom electrode is disposed over the barrier layer. The data storage feature is disposed over the bottom electrode. The top electrode is disposed over the data storage feature.

Abstract: A resistive memory device includes a bottom electrode, a switching layer disposed over the bottom electrode, a top electrode disposed over the switching layer, and an auxiliary layer disposed between the switching layer and one of the top electrode and the bottom electrode. The one of the top electrode and the bottom electrode includes a metal and is a relatively inert electrode in comparison with the other one of the top electrode and the bottom electrode. The auxiliary layer includes a nitride of the metal.

Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

Abstract: A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.

Abstract: An integrated circuit includes a metal/dielectric layer, a second dielectric layer, a bottom electrode, a resistance switch element, and a top electrode. The metal/dielectric layer has a first dielectric layer and a conductive feature in the first dielectric layer. The second dielectric layer is over the metal/dielectric layer. The bottom electrode is over and in contact with the conductive feature and surrounded by the second dielectric layer. The second dielectric layer has a tapered sidewall, a lower portion of the tapered sidewall of the second dielectric layer is covered by the bottom electrode, and an upper portion of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode. The resistance switch element is over the bottom electrode. The top electrode is over the resistance switch element.

Abstract: An integrated circuit structure includes a plurality of transistors, an interconnect layer, and a memory stack. The interconnect layer includes an interlayer dielectric (ILD) and a conductive structure embedded in the ILD. The conductive structure includes a barrier layer and a conductive filling material surrounded by the barrier layer in a cross-sectional view. The memory stack is over the interconnect layer. The memory stack includes a bottom electrode extending across the conductive structure in the cross-sectional view, a resistance switching layer over the bottom electrode, and a top electrode over the resistance switching layer. In the cross-sectional view, an interface formed by the bottom electrode and the barrier layer has a topmost point higher than a topmost point of an interface formed by the bottom electrode and the conductive filling material.

Abstract: A device structure includes a first metal interconnect structure formed in a first dielectric material layer; an etch-stop dielectric layer overlying the first dielectric material layer and having an opening having a first width along a first horizontal direction; and a resistive memory cell including a stack of a bottom electrode, a memory material layer, and a top electrode. The bottom electrode includes a plate portion and a via portion located within the opening in the etch-stop dielectric layer. The memory material layer overlies the bottom electrode and is configured to provide at least two states having different electrical resistance. The top electrode overlies the memory material layer. A hard mask plate overlies the top electrode. A periphery of a top surface of the hard mask plate has a second width along the first horizontal direction that is greater than the first width.

Abstract: A memory device includes a two-dimensional array of access transistors located on a semiconductor substrate; metal interconnect structures embedded in dielectric material layers and electrical connected to electrical nodes of the access transistors; and a two-dimensional array of resistive memory structures embedded in the dielectric material layers. The metal interconnect structures include two first source lines located at a first metal line level and laterally extending along a first horizontal direction; a second source line located at a second metal line level and laterally extending along the first horizontal direction; and a vertical connection structure including a plurality of interconnection via structures and at least one line-level metal structure and providing a vertical electrical connection between the two first source lines and the second source line.

Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: A semiconductor structure includes a ferroelectric layer and a semiconductor layer. Thee ferroelectric layer has a first surface and a second surface opposite to the first surface. The semiconductor layer is formed on one of the first surface and the second surface.

Abstract: The present disclosure provides a system for signal optimization adjustment based on different heat source information. The system includes a plurality of heat source measurers, a first system chip, a second system chip, an electrical interconnection, and a bit error risk evaluator. The first system chip includes a signal transmitter, and the second system chip includes a signal receiver. The second system chip provides an electrical characteristic state of the signal receiver, and a signal adjustment information of the signal transmitter and/or the signal receiver. The bit error risk evaluator performs a signal optimization adjustment for an electrical characteristic of the signal receiver according to the electrical characteristic state. The present disclosure further provides a method for signal optimization adjustment.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material on a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An insulating structure is arranged over and along opposing outermost sidewalls of the top electrode. The bottom electrode laterally extends to different non-zero distances past opposing outermost sidewalls of the insulating structure.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.

Abstract: Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.