Patents by Inventor Ting Chu

Ting Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190096795
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a memory cell on a homogeneous bottom electrode via (BEVA) top surface. In some embodiments, the integrated circuit comprises a conductive wire, a via dielectric layer, a via, and a memory cell. The via dielectric layer overlies the conductive wire. The via extends through the via dielectric layer to the conductive wire, and has a first sidewall, a second sidewall, and a top surface. The first and second sidewalls of the via are respectively on opposite sides of the via, and directly contact sidewalls of the via dielectric layer. The top surface of the via is homogenous and substantially flat. Further, the top surface of the via extends laterally from the first sidewall of the via to the second sidewall of the via. The memory cell is directly on the top surface of the via.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20190067373
    Abstract: In some embodiments, the present disclosure relates to a memory circuit having a first resistive random access memory (RRAM) element and a second RRAM element arranged within a dielectric structure over a substrate. The first RRAM element has a first conjunct electrode separated from a first disjunct electrode by a first data storage layer. The second RRAM element has a second conjunct electrode separated from a second disjunct electrode by a second data storage layer. A control device is disposed within the substrate and has first terminal coupled to the first conjunct electrode and the second conjunct electrode and a second terminal coupled to a word-line.
    Type: Application
    Filed: February 26, 2018
    Publication date: February 28, 2019
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20190058109
    Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
    Type: Application
    Filed: November 27, 2017
    Publication date: February 21, 2019
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
  • Publication number: 20190051032
    Abstract: A system for generating an animated life story of a person is shown. The system may capture an image of the person's face and generate a computer-animated simulation of the person's face. The computer-animated simulation of the person's face may be superimposed upon a computer-generated based on personal historical data of the person so that a computer-generated life story of the person from an earlier period of time to the present may be generated as a movie or slideshow.
    Type: Application
    Filed: February 24, 2017
    Publication date: February 14, 2019
    Inventors: Ting Chu, Jiancheng Xu
  • Publication number: 20190051702
    Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain of the FET has a higher doping concentration than the source of the FET. The resistive memory element is coupled with the drain via a portion of an interconnect structure.
    Type: Application
    Filed: October 15, 2018
    Publication date: February 14, 2019
    Inventors: Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20190043795
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a memory cell on a homogeneous bottom electrode via (BEVA) top surface. In some embodiments, the integrated circuit comprises a conductive wire, a via dielectric layer, a via, and a memory cell. The via dielectric layer overlies the conductive wire. The via extends through the via dielectric layer to the conductive wire, and has a first sidewall, a second sidewall, and a top surface. The first and second sidewalls of the via are respectively on opposite sides of the via, and directly contact sidewalls of the via dielectric layer. The top surface of the via is homogenous and substantially flat. Further, the top surface of the via extends laterally from the first sidewall of the via to the second sidewall of the via. The memory cell is directly on the top surface of the via.
    Type: Application
    Filed: September 26, 2017
    Publication date: February 7, 2019
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10199575
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device has a bottom electrode arranged over a bottom electrode via. A variable resistive dielectric layer is arranged over the bottom electrode. The variable resistive dielectric layer extends to within a recess in an upper surface of the bottom electrode. A top electrode is disposed over the variable resistive dielectric layer. A top electrode via extends outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the recess within the upper surface of the bottom electrode. The top electrode via has a smaller total width than the top electrode.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • Publication number: 20180374901
    Abstract: The present disclosure relates to a method of forming an integrated circuit. In some embodiments, the method may be performed by forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over an upper surface of a substrate, and forming a resistive random access memory (RRAM) device over the lower interconnect structure. A second ILD layer is formed over the RRAM device. The second ILD layer is patterned to remove a part of the second ILD layer that defines a cavity. The cavity vertically extends from an upper surface of the second ILD layer to an upper surface of the RRAM device and laterally extends past opposing sidewalls of the RRAM device. An upper interconnect wire is formed within the cavity.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 27, 2018
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20180375024
    Abstract: The present disclosure relates to an RRAM device having an electrode with an oxygen barrier structure, which is configured to improve RRAM reliability by mitigating oxygen movement and thereby maintaining oxygen within close proximity of a dielectric data storage layer, and an associated method of formation. In some embodiments, the RRAM device has a bottom electrode disposed over a lower interconnect layer surrounded by a ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom electrode, and a multi-layer top electrode disposed over the dielectric data storage layer. The multi-layer top electrode has conductive top electrode layers separated by an oxygen barrier structure configured to mitigate movement of oxygen within the multi-layer top electrode. By including an oxygen barrier structure within the top electrode, the reliability of the RRAM device is improved since oxygen is kept close to the dielectric data storage layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: December 27, 2018
    Inventors: Wen-Ting Chu, Tong-Chern Ong, Ying-Lang Wang
  • Publication number: 20180375022
    Abstract: The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Patent number: 10164169
    Abstract: The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Patent number: 10164094
    Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Jen-Sheng Yang, Sheng-Hung Shih, Tong-Chern Ong, Wen-Ting Chu
  • Patent number: 10163981
    Abstract: The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10164182
    Abstract: The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Patent number: 10164185
    Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10158070
    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10158072
    Abstract: A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Sheng Yang, Wen-Ting Chu, Chih-Yang Chang, Chin-Chieh Yang, Kuo-Chi Tu, Sheng-Hung Shih, Yu-Wen Liao, Hsia-Wei Chen, I-Ching Chen
  • Publication number: 20180351099
    Abstract: A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.
    Type: Application
    Filed: July 28, 2017
    Publication date: December 6, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Sheng YANG, Wen-Ting CHU, Chih-Yang CHANG, Chin-Chieh YANG, Kuo-Chi TU, Sheng-Hung SHIH, Yu-Wen LIAO, Hsia-Wei CHEN, I-Ching CHEN
  • Patent number: 10109793
    Abstract: The present disclosure relates to a memory cell having a multi-layer bottom electrode with an insulating core that provides for good gap fill ability, and an associated method of formation. In some embodiments, the memory cell includes a bottom electrode having an insulating material surrounded by a conductive material. A dielectric data storage layer is arranged over the bottom electrode, and a top electrode is arranged over the dielectric data storage layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10103330
    Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Yu-Wen Liao, Chin-Chieh Yang, Wen-Ting Chu