Patents by Inventor Ting-Chun Wang

Ting-Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210374552
    Abstract: Apparatuses, systems, and techniques are presented to synthesize consistent images or video. In at least one embodiment, one or more neural networks are used to generate one or more second images based, at least in part, on one or more point cloud representations of one or more first images.
    Type: Application
    Filed: June 1, 2020
    Publication date: December 2, 2021
    Inventors: Arun Mallya, Ting-Chun Wang, Ming-Yu Liu, Karan Spara
  • Publication number: 20210343709
    Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride liner is thicker than the first nitride liner.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chieh-Ping WANG, Tai-Chun HUANG, Yung-Cheng LU, Ting-Gang CHEN, Chi On CHUI
  • Patent number: 11157046
    Abstract: An electronic device is provided, including a main body, a cover movably connected to the main body, a biasing element connected to the cover and the main body, a movable member movably disposed on the main body, and a magnetic element disposed on the movable member. When the cover is located in a closed position relative to the main body, the cover is attracted by the magnetic element and restricted in the closed position. When the movable member is pushed by an external force to move from its initial position to a first position, the movable member and the magnetic element separate from the cover, and the biasing element drives the cover to move from the closed position to an open position.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 26, 2021
    Assignee: ACER INCORPORATED
    Inventors: Ting-Wen Pai, Wen-Chieh Tai, Cheng-Nan Ling, Chih-Chun Liu, Yu-Shih Wang
  • Publication number: 20210329306
    Abstract: Apparatuses, systems, and techniques to perform compression of video data using neural networks to facilitate video streaming, such as video conferencing. In at least one embodiment, a sender transmits to a receiver a key frame from video data and one or more keypoints identified by a neural network from said video data, and a receiver reconstructs video data using said key frame and one or more received keypoints.
    Type: Application
    Filed: October 13, 2020
    Publication date: October 21, 2021
    Inventors: Ming-Yu Liu, Ting-Chun Wang, Arun Mohanray Mallya, Tero Tapani Karras, Samuli Matias Laine, David Patrick Luebke, Jaakko Lehtinen, Miika Samuli Aittala, Timo Oskari Aila
  • Publication number: 20210313181
    Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: Ting-Gang Chen, Wan-Hsien Lin, Chieh-Ping Wang, Tai-Chun Huang, Chi On Chui
  • Publication number: 20210296472
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a dielectric structure over the substrate. The semiconductor device structure includes a contact structure passing through the dielectric structure. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer. The first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, the contact layer passes through the first barrier layer and extends into the dielectric structure, and the first barrier layer passes through the second barrier layer and extends into the dielectric structure.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yang WU, Shiu-Ko JANGJIAN, Ting-Chun WANG, Yung-Si YU
  • Patent number: 11122033
    Abstract: A method and system of authenticating a user are provided. A request for a resource is received by a server, from a user device. A predefined number is received from the user device. A first number and a second number are created. The first number is sent to the user device. A first discrete logarithm is determined based on a challenge code and the first number and sent to the user device. A first pass code is calculated via a second discrete logarithm based on the first discrete logarithm, the predefined number, and the first number. A second pass code based on the second discrete logarithm, is received from the user device. The first pass code is compared to the second pass code. Upon determining that the first pass code is identical to the second pass code, the user device is allowed access a resource associated with the computing device.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yi-Chun Chen, Wen-Ping Chi, Chao Yuan Huang, Ting-Yi Wang
  • Publication number: 20210279841
    Abstract: Apparatuses, systems, and techniques for texture synthesis from small input textures in images using convolutional neural networks. In at least one embodiment, one or more convolutional layers are used in conjunction with one or more transposed convolution operations to generate a large textured output image from a small input textured image while preserving global features and texture, according to various novel techniques described herein.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 9, 2021
    Inventors: Guilin Liu, Andrew Tao, Bryan Christopher Catanzaro, Ting-Chun Wang, Zhiding Yu, Shiqiu Liu, Fitsum Reda, Karan Sapra, Brandon Rowlett
  • Publication number: 20210280572
    Abstract: An integrated circuit includes a first gate electrode structure extending in a first direction and having a first portion and a second portion separated from each other. The integrated circuit further includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit further includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, wherein the first section extends in the second direction. The conductive feature further includes a second section electrically connected to the second gate electrode structure, wherein the second section extends in the second direction. The conductive feature further includes a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.
    Type: Application
    Filed: May 11, 2021
    Publication date: September 9, 2021
    Inventors: Tung-Heng HSIEH, Ting-Wei CHIANG, Chung-Te LIN, Hui-Zhong ZHUANG, Li-Chun TIEN, Sheng-Hsiung WANG
  • Publication number: 20210273106
    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Cheng-Ta WU, Cheng-Wei CHEN, Shiu-Ko JANGJIAN, Ting-Chun WANG
  • Publication number: 20210238765
    Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.
    Type: Application
    Filed: April 22, 2021
    Publication date: August 5, 2021
    Inventors: Jun-Nan NIAN, Shiu-Ko JANGJIAN, Yu-Ren PENG, Yao-Hsiang LIANG, Ting-Chun WANG
  • Patent number: 11031488
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor over a substrate. The semiconductor device structure includes a dielectric structure over the substrate and covering the transistor. The semiconductor device structure includes a contact structure passing through the dielectric structure and electrically connected to the transistor. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Ting-Chun Wang, Yung-Si Yu
  • Patent number: 11024716
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Yi-Hsien Lee, Wei-Ming You, Ting-Chun Wang
  • Patent number: 11015260
    Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Nan Nian, Shiu-Ko Jangjian, Yu-Ren Peng, Yao-Hsiang Liang, Ting-Chun Wang
  • Publication number: 20210150354
    Abstract: A latent code defined in an input space is processed by the mapping neural network to produce an intermediate latent code defined in an intermediate latent space. The intermediate latent code may be used as appearance vector that is processed by the synthesis neural network to generate an image. The appearance vector is a compressed encoding of data, such as video frames including a person's face, audio, and other data. Captured images may be converted into appearance vectors at a local device and transmitted to a remote device using much less bandwidth compared with transmitting the captured images. A synthesis neural network at the remote device reconstructs the images for display.
    Type: Application
    Filed: January 7, 2021
    Publication date: May 20, 2021
    Inventors: Tero Tapani Karras, Samuli Matias Laine, David Patrick Luebke, Jaakko T. Lehtinen, Miika Samuli Aittala, Timo Oskari Aila, Ming-Yu Liu, Arun Mohanray Mallya, Ting-Chun Wang
  • Publication number: 20210150187
    Abstract: A latent code defined in an input space is processed by the mapping neural network to produce an intermediate latent code defined in an intermediate latent space. The intermediate latent code may be used as appearance vector that is processed by the synthesis neural network to generate an image. The appearance vector is a compressed encoding of data, such as video frames including a person's face, audio, and other data. Captured images may be converted into appearance vectors at a local device and transmitted to a remote device using much less bandwidth compared with transmitting the captured images. A synthesis neural network at the remote device reconstructs the images for display.
    Type: Application
    Filed: January 7, 2021
    Publication date: May 20, 2021
    Inventors: Tero Tapani Karras, Samuli Matias Laine, David Patrick Luebke, Jaakko T. Lehtinen, Miika Samuli Aittala, Timo Oskari Aila, Ming-Yu Liu, Arun Mohanray Mallya, Ting-Chun Wang
  • Patent number: 11011641
    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Shiu-Ko Jangjian, Ting-Chun Wang
  • Patent number: 10998194
    Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • Publication number: 20210125935
    Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.
    Type: Application
    Filed: January 4, 2021
    Publication date: April 29, 2021
    Inventors: Chia-Yang Wu, Shiu-Ko JangJian, Ting-Chun Wang, Yung-Si Yu
  • Patent number: 10984286
    Abstract: A style transfer neural network may be used to generate stylized synthetic images, where real images provide the style (e.g., seasons, weather, lighting) for transfer to synthetic images. The stylized synthetic images may then be used to train a recognition neural network. In turn, the trained neural network may be used to predict semantic labels for the real images, providing recognition data for the real images. Finally, the real training dataset (real images and predicted recognition data) and the synthetic training dataset are used by the style transfer neural network to generate stylized synthetic images. The training of the neural network, prediction of recognition data for the real images, and stylizing of the synthetic images may be repeated for a number of iterations. The stylization operation more closely aligns a covariate of the synthetic images to the covariate of the real images, improving accuracy of the recognition neural network.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: April 20, 2021
    Assignee: NVIDIA Corporation
    Inventors: Aysegul Dundar, Ming-Yu Liu, Ting-Chun Wang, John Zedlewski, Jan Kautz