Patents by Inventor Ting-Chun Wang

Ting-Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9577102
    Abstract: A method of forming a gate includes: forming a dummy gate; forming an inter layer dielectric (ILD) laterally adjacent to the dummy gate; doping a dopant into the dummy gate and the ILD, in which a surface dopant concentration of the dummy gate is lower than a surface dopant concentration of the ILD; removing the dummy gate to form a cavity after doping the dopant into the dummy gate and the ILD; and forming the gate in the cavity.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: February 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ting Hsiao, Cheng-Ta Wu, Lun-Kuang Tan, Liang-Yu Yen, Ting-Chun Wang, Tsung-Han Wu, Wei-Ming You
  • Publication number: 20170047420
    Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.
    Type: Application
    Filed: October 27, 2016
    Publication date: February 16, 2017
    Inventors: Sheng-Wen Chen, Yu-Ting Lin, Che-Hao Chang, Wei-Ming You, Ting-Chun Wang
  • Publication number: 20170040456
    Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 9, 2017
    Inventors: Shiu-Ko JANGJIAN, Chi-Cherng JENG, Chih-Nan WU, Chun-Che LIN, Ting-Chun WANG
  • Publication number: 20170032970
    Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 2, 2017
    Inventors: Cheng-Ta WU, Shiu-Ko JANGJIAN, Chung-Ren SUN, Ming-Te CHEN, Ting-Chun WANG, Jun-Jie CHENG
  • Publication number: 20170033199
    Abstract: A semiconductor device includes a semiconductor fin, a first silicon nitride based layer, a lining oxide layer, a second silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The first silicon nitride based layer peripherally encloses the second side surface of the semiconductor fin. The lining oxide layer is disposed conformal to the first silicon nitride based layer. The second silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface of the semiconductor fin.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Cheng-Ta WU, Ting-Chun WANG, Yuan-Nien CHEN
  • Publication number: 20170025535
    Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.
    Type: Application
    Filed: July 21, 2015
    Publication date: January 26, 2017
    Inventors: Cheng-Ta WU, Ting-Chun WANG, Wei-Ming YOU, J.W. WU
  • Patent number: 9543234
    Abstract: A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Szu-An Wu, Ting-Chun Wang
  • Patent number: 9508548
    Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Wen Chen, Yu-Ting Lin, Che-Hao Chang, Wei-Ming You, Ting-Chun Wang
  • Patent number: 9478581
    Abstract: A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Ting-Chun Wang, Chung-Ren Sun
  • Patent number: 9478660
    Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiu-Ko Jangjian, Chi-Cherng Jeng, Chih-Nan Wu, Chun-Che Lin, Ting-Chun Wang
  • Publication number: 20160307895
    Abstract: A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventors: CHENG-TA WU, CHENG-WEI CHEN, HONG-YI WU, SHIU-KO JANGJIAN, WEI-MING YOU, TING-CHUN WANG
  • Publication number: 20160308059
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 20, 2016
    Inventors: CHENG-TA WU, YI-HSIEN LEE, WEI-MING YOU, TING-CHUN WANG
  • Publication number: 20160254122
    Abstract: The present disclosure provides a method for generating a parameter pattern including: performing a plurality of measurements upon a plurality of regions on a surface of a workpiece to obtain a plurality of measured results; and deriving a parameter pattern according to the plurality of measured results by a computer; wherein the parameter pattern includes a plurality of regional parameter values corresponding to each of the plurality of regions on the surface of the workpiece. The present disclosure provides a Feed Forward semiconductor manufacturing method including: forming a layer with a desired pattern on a surface of a workpiece; deriving a control signal including a parameter pattern according to spatial dimension measurements against the layer with the desired pattern distributed over a plurality of regions of the surface of the workpiece; and performing an ion implantation on the surface of the workpiece according to the control signal.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: CHENG-TA WU, TSUNG HAN WU, YAO-WEN HSU, LUN-KUANG TAN, WEI-MING YOU, TING-CHUN WANG
  • Publication number: 20160254157
    Abstract: A method includes forming a gate stack over a semiconductor substrate; forming an interlayer dielectric layer surrounding the gate stack; and at least partially removing the gate stack, thereby forming an opening. The method further includes forming a multi-function wetting/blocking layer in the opening, a work function layer over the multi-function blocking/wetting layer, and a conductive layer over the work function layer. The work function layer, the multi-function wetting/blocking layer, and the conductive layer fill the opening. The multi-function wetting/blocking layer includes aluminum, carbon, nitride, and one of: titanium and tantalum.
    Type: Application
    Filed: May 9, 2016
    Publication date: September 1, 2016
    Inventors: SHIU-KO JANGJIAN, TING-CHUN WANG, CHI-CHERNG JENG, CHI-WEN LIU
  • Patent number: 9406675
    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes providing a substrate, forming a fin structure extruding from the substrate, forming shallow trench isolations over the substrate, and forming an oxide material over the fin structure. The method further includes forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer over the oxide material, wherein the forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer includes doping carbon in a range of from about 5E19/cm3 to about 1E22/cm3.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Hong-Yi Wu, Shiu-Ko Jangjian, Wei-Ming You, Ting-Chun Wang
  • Publication number: 20160204245
    Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.
    Type: Application
    Filed: April 2, 2015
    Publication date: July 14, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shiu-Ko JANGJIAN, Chi-Cherng JENG, Chih-Nan WU, Chun-Che LIN, Ting-Chun WANG
  • Publication number: 20160190305
    Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate; wherein the gate stack includes a high k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack has a convex top surface.
    Type: Application
    Filed: April 15, 2015
    Publication date: June 30, 2016
    Inventors: Shiu-Ko JangJian, Chih-Nan Wu, Chun Che Lin, Ting-Chun Wang
  • Publication number: 20160173869
    Abstract: An apparatus comprises a main camera configured to produce a high quality image; at least two auxiliary cameras configured to produce images of lower quality; and electronic circuitry linked to the main camera and the at least two auxiliary cameras, the electronic circuitry comprising a controller having a memory and a processor, the electronic circuitry configured to operate on data pertaining to the high quality image and pertaining to the images of lower quality to produce an enhanced high quality image as output data.
    Type: Application
    Filed: December 15, 2014
    Publication date: June 16, 2016
    Inventors: Ting-Chun Wang, Manohar Srikanth
  • Publication number: 20160155771
    Abstract: A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Ting-Chun Wang, Chung-Ren Sun
  • Patent number: 9337303
    Abstract: A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jangjian, Chi-Wen Liu, Chi-Cherng Jeng, Ting-Chun Wang