Patents by Inventor Ting-Chun Wang

Ting-Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9337303
    Abstract: A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jangjian, Chi-Wen Liu, Chi-Cherng Jeng, Ting-Chun Wang
  • Patent number: 9337192
    Abstract: An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • Patent number: 9257476
    Abstract: A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Ting-Chun Wang, Chung-Ren Sun
  • Publication number: 20150372099
    Abstract: A substrate is provided. The substrate has a source/drain region formed therein and a dielectric layer formed thereover. A contact hole is etched in the dielectric layer to expose a portion of the source/drain region. A metal material is formed on the source/drain region exposed by the opening. A first annealing process is performed to facilitate a reaction between the metal material and the portion of the source/drain region disposed therebelow, thereby forming a metal silicide in the substrate. The first annealing process is a spike annealing process. A remaining portion of the metal material is removed after the performing of the first annealing process. Thereafter, a second annealing process is performed. Thereafter, a contact is formed in the contact hole, the contact being formed on the metal silicide.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 24, 2015
    Inventors: Sheng-Wen Chen, Yu-Ting Lin, Jemmy Tsai, Wei-Ming You, Ting-Chun Wang
  • Publication number: 20150357421
    Abstract: Some embodiments relate to a silicon wafer having a disc-like silicon body. The wafer includes a central portion circumscribed by a circumferential edge region. A plurality of sampling locations, which are arranged in the circumferential edge region, have a plurality of wafer property values, respectively, which correspond to a wafer property. The plurality of wafer property values differ from one another according to a pre-determined statistical edge region profile.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 10, 2015
    Inventors: I-Che Huang, Pu-Fang Chen, Ting-Chun Wang
  • Publication number: 20150279954
    Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Inventors: Sheng-Wen Chen, Yu-Ting Lin, Che-Hao Chang, Wei-Ming You, Ting-Chun Wang
  • Publication number: 20150236067
    Abstract: A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Ting-Chun Wang, Chung-Ren Sun
  • Patent number: 9064823
    Abstract: A method is provided for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. A plurality of locations are defined about a periphery of the semiconductor wafer, and one or more properties, such as oxygen concentration and a density of bulk micro defects present, are measured at each of the plurality of locations. A statistical profile associated with the periphery of the semiconductor wafer is determined based on the one or more properties measured at the plurality of locations. The semiconductor wafer is subsequently thermally treated when the statistical profile falls within a predetermined range. The semiconductor wafer is rejected from subsequent processing when the statistical profile deviates from the predetermined range. As such, wafers prone to distortion, warpage, and breakage are rejected from subsequent thermal processing.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Che Huang, Pu-Fang Chen, Ting-Chun Wang
  • Patent number: 9041140
    Abstract: A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Ting-Chun Wang, Chung-Ren Sun
  • Publication number: 20150115450
    Abstract: A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 30, 2015
    Inventors: Shiu-Ko JangJian, Szu-An Wu, Ting-Chun Wang
  • Publication number: 20150085162
    Abstract: A perceptual radiometric compensation system adaptable to a projector-camera system includes a brightness scaling unit that scales down brightness of an input image and obtains appearance attributes by a color appearance model (CAM). A hue adjustment unit adjusts hue of the input image toward tone of a colored projection surface by the CAM.
    Type: Application
    Filed: August 22, 2014
    Publication date: March 26, 2015
    Inventors: Tai-Hsiang HUANG, Ting-Chun Wang, Kuang-Tsu Shih, Homer H. CHEN
  • Publication number: 20150054029
    Abstract: An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Inventors: SHIU-KO JANGJIAN, TING-CHUN WANG, CHI-CHERNG JENG, CHI-WEN LlU
  • Patent number: 8946083
    Abstract: A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Ting-Chun Wang, Szu-An Wu
  • Publication number: 20140319626
    Abstract: A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Shiu-Ko Jangjian, Chi-Wen Liu, Chi-Cherng Jeng, Ting-Chun Wang
  • Publication number: 20140273291
    Abstract: A method is provided for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. A plurality of locations are defined about a periphery of the semiconductor wafer, and one or more properties, such as oxygen concentration and a density of bulk micro defects present, are measured at each of the plurality of locations. A statistical profile associated with the periphery of the semiconductor wafer is determined based on the one or more properties measured at the plurality of locations. The semiconductor wafer is subsequently thermally treated when the statistical profile falls within a predetermined range. The semiconductor wafer is rejected from subsequent processing when the statistical profile deviates from the predetermined range. As such, wafers prone to distortion, warpage, and breakage are rejected from subsequent thermal processing.
    Type: Application
    Filed: May 8, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Che Huang, Pu-Fang Chen, Ting-Chun Wang
  • Patent number: 8748885
    Abstract: A semiconductor device including a first wafer assembly having a first substrate and a first oxide layer over the first substrate. The semiconductor device further includes a second wafer assembly having a second substrate and a second oxide layer over the second substrate. The first oxide layer and the second oxide layer are bonded together by van der Waals bonds or covalent bonds. A method of bonding a first wafer assembly and a second wafer assembly including forming a first oxide layer over a first substrate. The method further includes forming a second oxide layer over a second wafer assembly. The method further includes forming van der Waals bonds or covalent bonds between the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ti Yeh, Chung-Yi Huang, Ya Wen Wu, Hui Mei Jao, Ting-Chun Wang, Shiu-Ko JangJian, Chia-Hung Chung
  • Patent number: 8592297
    Abstract: A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ti Yeh, Wu-Chang Lin, Chung-Yi Huang, Ya Wen Wu, Hui-Mei Jao, Ting-Chun Wang, Chia-Hung Chung
  • Publication number: 20130241018
    Abstract: A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Ting-Chun Wang, Chung-Ren Sun
  • Publication number: 20130207098
    Abstract: A semiconductor device including a first wafer assembly having a first substrate and a first oxide layer over the first substrate. The semiconductor device further includes a second wafer assembly having a second substrate and a second oxide layer over the second substrate. The first oxide layer and the second oxide layer are bonded together by van der Waals bonds or covalent bonds. A method of bonding a first wafer assembly and a second wafer assembly including forming a first oxide layer over a first substrate. The method further includes forming a second oxide layer over a second wafer assembly. The method further includes forming van der Waals bonds or covalent bonds between the first oxide layer and the second oxide layer.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Ti YEH, Chung-Yi HUANG, Ya Wen WU, Hui-Mei JAO, Ting-Chun WANG, Shiu-Ko JiangJian, Chia-Hung CHUNG
  • Publication number: 20130154060
    Abstract: A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Ti YEH, Wu-Chang LIN, Chung-Yi HUANG, Ya Wen WU, Hui-Mei JAO, Ting-Chun WANG, Chia-Hung CHUNG