Patents by Inventor Ting Fan

Ting Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180337032
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Patent number: 10109477
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 23, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Publication number: 20180166582
    Abstract: A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.
    Type: Application
    Filed: March 2, 2017
    Publication date: June 14, 2018
    Inventors: Yu-Hung LIAO, Samuel C. PAN, Sheng-Ting FAN, Min-Hung LEE, Chee-Wee LIU
  • Patent number: 9919073
    Abstract: The disclosed hydrophobic adhesive composition comprises a hydrophobic adhesive matrix and water absorbent fibers dispersed throughout the adhesive matrix to provide water management capabilities to the adhesive composition. The disclosed adhesive composition can adhered to a variety of surfaces, such as skin, and will easily remove from the surface. Therefore, the disclosed adhesive is particularly well suitable for application to skin wherein the absorbent fiber can absorb perspiration, water, or wound fluid from skin.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: March 20, 2018
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Junkang J. Liu, Cary A. Kipke, Ting Fan
  • Publication number: 20180038865
    Abstract: The present invention provides a method for detecting and treating hematologic malignancies including leukemia such as acute lymphoblastic leukemia (ALL) in a subject and a method for determining disease prognosis among leukemia patients by detecting CD9 expression. A kit and device useful for such methods are also provided. In addition, the present invention provides a composition for treating hematologic malignancies such as leukemia by suppressing CD9 expression or activity.
    Type: Application
    Filed: July 18, 2017
    Publication date: February 8, 2018
    Inventors: Kam Tong Leung, Chi Kong Li, Pak Cheung Ng, Karen Li, Ting Fan Leung, Yuen Yee Kathy Chan
  • Publication number: 20170194470
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Application
    Filed: May 10, 2016
    Publication date: July 6, 2017
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Patent number: 9601202
    Abstract: The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM, in addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: March 21, 2017
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Ya-Ting Fan, Chia-Hao Tai, Tung-Yu Yeh
  • Publication number: 20170040418
    Abstract: Semiconductor devices and methods of forming the same are provided. A first gate electrode layer is formed over a substrate. A first gate dielectric layer is formed over the first gate electrode layer. A first channel layer is formed over the first gate dielectric layer. An isolation layer is formed over the first channel layer. A second channel layer is formed over the isolation layer. A second gate dielectric layer is formed over the second channel layer. The second gate dielectric layer, the second channel layer, the isolation layer and the first channel layer are patterned to form a first opening, the first opening extending through the first gate dielectric layer, the second channel layer and the isolation layer, and into the first channel layer. A first source/drain region is formed in the first opening.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Pin-Shiang Chen, Samuel C. Pan, Chee-Wee Liu, Sheng-Ting Fan
  • Publication number: 20160379712
    Abstract: The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM, in addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.
    Type: Application
    Filed: September 8, 2016
    Publication date: December 29, 2016
    Inventors: HSIN-CHANG LIN, WEN-CHIEN HUANG, YA-TING FAN, CHIA-HAO TAI, TUNG-YU YEH
  • Publication number: 20160329104
    Abstract: The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM. In addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.
    Type: Application
    Filed: May 8, 2015
    Publication date: November 10, 2016
    Inventors: HSIN-CHANG LIN, WEN-CHIEN HUANG, YA-TING FAN, CHIA-HAO TAI, TUNG-YU YEH
  • Patent number: 9490430
    Abstract: Semiconductor devices and methods of forming the same are provided. A first gate electrode layer is formed over a substrate. A first gate dielectric layer is formed over the first gate electrode layer. A first channel layer is formed over the first gate dielectric layer. An isolation layer is formed over the first channel layer. A second channel layer is formed over the isolation layer. A second gate dielectric layer is formed over the second channel layer. The second gate dielectric layer, the second channel layer, the isolation layer and the first channel layer are patterned to form a first opening, the first opening extending through the first gate dielectric layer, the second channel layer and the isolation layer, and into the first channel layer. A first source/drain region is formed in the first opening.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: November 8, 2016
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Pin-Shiang Chen, Samuel C. Pan, Chee-Wee Liu, Sheng-Ting Fan
  • Patent number: 9318208
    Abstract: A method for operating a small-area EEPROM array is disclosed. The small-area EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line. The common source lines include a first common source line. Each sub-memory array includes a first, second, third and fourth memory cells, which are connected with two bit line groups, a word line and a common source line. The first and second memory cells are symmetric. The third and fourth memory cells are symmetric. The group of the first and second memory cells and the group of the third and fourth memory cells are respectively positioned at two sides of the first common source line. The method operates all operation memory cells and uses special biases to program or erase memory cells massively in a single operation.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 19, 2016
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Ya-Ting Fan, Yang-Sen Yeh, Cheng-Ying Wu
  • Patent number: 9281312
    Abstract: A non-volatile memory with a single gate-source common terminal and an operation method thereof are provided. The non-volatile memory includes a transistor and a capacitor structure both embedded in a semiconductor substrate. The transistor includes a first dielectric layer, a first electric-conduction gate and several first ion-doped regions. The capacitor structure includes a second dielectric layer, a second electric-conduction gate and a second ion-doped region. The memory may further include a third ion-doped region below the second dielectric layer. The first and second electric-conduction gates are electrically connected to form a single floating gate of the memory cell. The source and second ion-doped region are electrically connected to form a single gate-source common terminal.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: March 8, 2016
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Ya-Ting Fan, Wen-Chien Huang
  • Patent number: 9240242
    Abstract: A method for operating a low-cost EEPROM array is disclosed. The EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line and a second word line. The common source lines include a first common source line. Each sub-memory array includes a first memory cell and a second memory cell, which are respectively connected with the first and second word lines. Each of the first and second memory cells is also connected with the first bit line group and the first common source line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method operates all the operation memory cells and uses special biases to program or erase memory cells massively in a single operation.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: January 19, 2016
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Ya-Ting Fan, Yang-Sen Yeh, Cheng-Ying Wu
  • Publication number: 20160013194
    Abstract: The present invention discloses a non-volatile memory with a single gate-source common terminal and an operation method thereof. The non-volatile memory comprises a transistor and a capacitor structure both embedded in a semiconductor substrate. The transistor includes a first dielectric layer, a first electric-conduction gate and several first ion-doped regions. The capacitor structure includes a second dielectric layer, a second electric-conduction gate and a second ion-doped region. The memory may further comprise a third ion-doped region below the second dielectric layer. The first and second electric-conduction gates are electrically connected to form a single floating gate of the memory cell. The source and second ion-doped region are electrically connected to form a single gate-source common terminal. The present invention greatly decreases the area and control lines of the memory cell and thus effectively reduces the cost thereof.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 14, 2016
    Inventors: HSIN-CHANG LIN, YA-TING FAN, WEN-CHIEN HUANG
  • Publication number: 20150290045
    Abstract: A wound dressing comprising a base film layer which is made of polymer and have a grid pattern on one surface of the substrate layer is provided. A method of making the wound dressing comprising the steps of coating a polymer solution on a patterned liner and drying the polymer solution is also provided.
    Type: Application
    Filed: July 28, 2011
    Publication date: October 15, 2015
    Applicant: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Ting Fan, Jing Huang, JING Ma, JANE Hu
  • Publication number: 20150177232
    Abstract: A clinical specimen detector includes a clip having a clamping end and a pressing end; and wherein a pair of compressing slices are disposed on the clamping end, and a channel is disposed in the lower end of at least one of the pair of compressing slices. A detecting reagent test chip is attached to the outer surface of the compressing slice. The lower end of the detecting reagent test chip is substantially aligned with and is adjacent to the channel. The lower ends of the compressing slices clamp an adsorptive material adsorbed with body fluid such that the body fluid can be released from the adsorptive material because of the compression of the compressing slices and can be delivered to the lower end of the detecting reagent test chip via the channel, so as to perform disease testing and physiological condition testing with the detecting reagent test chip.
    Type: Application
    Filed: April 20, 2014
    Publication date: June 25, 2015
    Applicant: National Tsing Hua University
    Inventors: Hsi-Kai Wang, Shu-Ting Fan, Hong-Ren Lin, Ting-Chang Chang, Chia-Chi Wu, Chao-Min Cheng
  • Patent number: 9061969
    Abstract: A compound of formula (I) is disclosed: wherein definitions of R1, R2, and R3 are the same as those defined in the specification. The compound of formula (I) can emit light via an intramolecular interaction of an imino group and an electron-donatable moiety contained in the compound. A photoluminescent organic composition is also disclosed, which includes a compound represented by formula (II) in the presence of an electron-donatable compound, wherein definitions of R4, R5, and R6 are the same as those defined in the specification. The photoluminescent organic composition can emit light via an intermolecular interaction of an imino group contained in the compound of formula (II) and an electron-donatable moiety contained in the electron-donatable compound.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: June 23, 2015
    Assignee: I SHOU UNIVERSITY
    Inventors: Jau-Yann Wu, Pei-Ying Tsai, I-Hsiang Wang, Shi-Xuan Chou, Guan-Ru Pan, Shih-Han Wang, Ting-Fan Chou, Ming-Yao Huang, Yu-Cheng Wang
  • Publication number: 20150157302
    Abstract: The present invention discloses a clinical specimen sampler, including a filtering device; and a sampling device. The sampling device includes a sampling adsorber and a rod. The sampling adsorber is connected with one end of the rod, and the sampling adsorber is encompassed in the filtering device. The sampling adsorber is utilized to absorb the body fluid secreted by the intima of an organ, and the filtering device is employed to prevent the mucosal tissue of the intima of the organ from entering the sampling adsorber and enable the body fluid secreted by the intima of the organ to enter the sampling adsorber, so as to be absorbed by the sampling adsorber.
    Type: Application
    Filed: April 22, 2014
    Publication date: June 11, 2015
    Applicant: National Tsing Hua University
    Inventors: Shu-Ting FAN, Hsi-Kai WANG, Hong-Ren Lin, Ting-Chang Chang, Chia-Chi Wu, Chao-Min Cheng
  • Publication number: 20150037276
    Abstract: The present invention provides a hydrocolloid composition which, based on 100% by weight of the hydrocolloid composition, comprises: 10-90%) by weight of a polyisobutylene tackifier; 5-55% by weight of a hydrophilic absorbing substance; and 0.1-20% by weight of a functional ingredient. The invention further provides an article containing the hydrocolloid composition.
    Type: Application
    Filed: November 8, 2011
    Publication date: February 5, 2015
    Applicant: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Ting Fan, Ying Wei Xie, Jing Huang, Kai Qiu, Grace Ho, Dong Wu, Jie Hu