Patents by Inventor Ting Fan
Ting Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140364365Abstract: A mask for skin care includes a fiber substrate, wherein the fiber substrate is woven or nonwoven, and includes modified fibers, and the modified fibers are cellulose fibers with at least one hydrophilic functional group grafted on. The grafted ratio of the modified fibers is in the range from 5% to 30%, and the modified fibers can effectively improve the moisture absorption and the moisture-retaining capacity of the mask for skin care.Type: ApplicationFiled: March 17, 2014Publication date: December 11, 2014Applicant: Far Eastern New Century CorporationInventors: Yong-Yi Wu, Mei-Ting Fan Chiang, Zij-Jyun Fang
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Publication number: 20140220843Abstract: The disclosed hydrophobic adhesive composition comprises a hydrophobic adhesive matrix and water absorbent fibers dispersed throughout the adhesive matrix to provide water management capabilities to the adhesive composition. The disclosed adhesive composition can adhered to a variety of surfaces, such as skin, and will easily remove from the surface. Therefore, the disclosed adhesive is particularly well suitable for application to skin wherein the absorbent fiber can absorb perspiration, water, or wound fluid from skin.Type: ApplicationFiled: August 17, 2012Publication date: August 7, 2014Applicant: 3M INNOVATIVE PROPERTIES COMPANYInventors: Junkang J. Liu, Cary A. Kipke, Ting Fan
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Publication number: 20130334586Abstract: A non-self-aligned non-volatile memory structure, comprising: a semiconductor substrate; a left floating gate memory cell and a right floating gate memory cell; a control gate; and a gate insulation layer disposed among said two floating gate memory cells and said control gate. Drains of said two floating gate memory cells are connected to different voltage levels. Said control gate is over said two floating gate memory cells, to cover said floating gates of said two floating gate memory cells, so as to control said two floating gates simultaneously. Said non-self-aligned non-volatile memory structure mentioned above does not require line-to-line alignment of gates, thus reducing significantly the complexity of manufacturing process, and number of layers of photo masks required, in achieving production cost reduction.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Applicant: YIELD MICROELECTRONICS CORP.Inventors: HSIN CHANG LIN, WEN CHIEN HUANG, YA-TING FAN
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Publication number: 20130181276Abstract: A non-self aligned non-volatile memory structure includes a semiconductor substrate; a first gate insulation layer on said semiconductor substrate; a floating gate on first gate insulation layer; two doped regions in said semiconductor substrate, which are respectively on two sides of said first gate insulation layer, and adjoining said first gate insulation layer; a second gate insulation layer on said floating gate; and a control gate on said second gate insulation layer. Width of said control gate on said floating gate is less than that of said floating gate, and width of said control gate not on said floating gate is equal to or greater than width of said floating gate. Through the two non-self aligned gates, the non-volatile memory does not need to meet the requirement of gate line-to-line alignment, thus reducing complexity and cost of manufacturing process.Type: ApplicationFiled: January 17, 2012Publication date: July 18, 2013Applicant: YIELD MICROELECTRONICS CORP.Inventors: HSIN CHANG LIN, WEN CHIEN HUANG, YA-TING FAN
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Patent number: 8366417Abstract: A fan housing capable of anti-backflow includes a frame and a plurality of anti-backflow sheets. The frame has a plurality of fixing parts disposed at an opening of an outlet side of the frame. The anti-backflow sheets are respectively pivoted to the fixing parts and cover the opening on the outlet side of the frame. A fan having the fan housing capable of anti-backflow is also disclosed.Type: GrantFiled: October 11, 2007Date of Patent: February 5, 2013Assignee: Delta Electronics, Inc.Inventors: Jui-Ting Fan, Cheng-Shu Yu, Peng-Chu Tao
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Publication number: 20120316314Abstract: A water-insoluble polyglutamic acid (PGA) fiber and a preparation method thereof are provided. In the preparation method, the PGA is cross-linked by a cross-linking agent and then passes through a spinning nozzle to form PGA fibers. Therefore, the highly water-absorbing PGA, which cannot be spun by conventional methods, can be spun to form PGA fibers and maintain the high water-absorption ability.Type: ApplicationFiled: August 23, 2012Publication date: December 13, 2012Applicant: FAR EASTERN NEW CENTURY CORPORATIONInventors: Jo-Wei Huang, Mei-Ting Fan Chiang, Ken-Yuan Chang
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Publication number: 20120308636Abstract: A multi-layer antimicrobial wound dressing includes a wound-contacting layer and an antimicrobial layer. The wound contacting layer includes a biocompatible fibrous matrix that is made of an anionic polymer, and the antimicrobial layer is made of a cationic polymer that is connected to the wound-contacting layer via anionic-cationic interaction between the anionic polymer of the fibrous matrix and the cationic polymer of the antimicrobial layer.Type: ApplicationFiled: May 30, 2012Publication date: December 6, 2012Applicant: FAR EASTERN NEW CENTURY CORPORATIONInventors: Jo-Wei Huang, Mei-Ting Fan Chiang
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Patent number: 8305808Abstract: A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines.Type: GrantFiled: August 12, 2010Date of Patent: November 6, 2012Assignee: Yield Microelectronics Corp.Inventors: Hsin Chang Lin, Chia-Hao Tai, Yang-Sen Yen, Ming-Tsang Yang, Ya-Ting Fan
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Patent number: 8300461Abstract: An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit line and a second group bit line; the word line includes a first word line; and the common source lines include a first common source line. In addition, a plurality of sub-memory arrays are provided. Each sub-memory array contains a first, second, third, and fourth memory cells. Wherein, the first and second memory cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged; also, the first and second memory cells, and the third and fourth memory cells are symmetrically arranged with the first common source line as a symmetric axis.Type: GrantFiled: August 24, 2010Date of Patent: October 30, 2012Assignee: Yield Microelectronics Corp.Inventors: Hsin Chang Lin, Chia-Hao Tai, Yang-Sen Yen, Ming-Tsang Yang, Ya-Ting Fan
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Patent number: 8300469Abstract: A cost saving EEPROM array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines contain a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.Type: GrantFiled: August 11, 2010Date of Patent: October 30, 2012Assignee: Yield Microelectronics Corp.Inventors: Hsin Chang Lin, Chia-Hao Tai, Yang-Sen Yen, Ming-Tsang Yang, Ya-Ting Fan
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Publication number: 20120267573Abstract: A method for making a fluorescent gold nano-material having a gold nanocluster and thiol ligands on a surface of the gold nanocluster includes reacting a mixture of a gold-containing compound, an alkyl alcohol, and a thiol compound.Type: ApplicationFiled: November 10, 2011Publication date: October 25, 2012Inventors: Jau-Yann WU, Ting-Fan Chou, Huy-Zu Cheng, Shih-Han Wang, Li-Feng Liu, Chih-Yu Wang, Jia-Jung Wang, Wan-Nan U Chen, Chien-Fu Huang, Shen-Li Fu, Ta-Nung Hsieh
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Publication number: 20120267572Abstract: A compound of formula (I) is disclosed: wherein definitions of R1, R2, and R3 are the same as those defined in the specification. The compound of formula (I) can emit light via an intramolecular interaction of an imino group and an electron-donatable moiety contained in the compound. A photoluminescent organic composition is also disclosed, which includes a compound represented by formula (II) in the presence of an electron-donatable compound, wherein definitions of R4, R5, and R6 are the same as those defined in the specification. The photoluminescent organic composition can emit light via an intermolecular interaction of an imino group contained in the compound of formula (II) and an electron-donatable moiety contained in the electron-donatable compound.Type: ApplicationFiled: November 4, 2011Publication date: October 25, 2012Inventors: Jau-Yann WU, Pei-Ying Tsai, I-Hsiang Wang, Shi-Xuan Chou, Guan-Ru Pan, Shih-Han Wang, Ting-Fan Chou, Ming-Yao Huang, Yu-Cheng Wang
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Patent number: 8273278Abstract: A water-insoluble polyglutamic acid (PGA) fiber and a preparation method thereof are provided. In the preparation method, the PGA is cross-linked by a cross-linking agent and then passes through a spinning nozzle to form PGA fibers. Therefore, the highly water-absorbing PGA, which cannot be spun by conventional methods, can be spun to form PGA fibers and maintain the high water-absorption ability.Type: GrantFiled: April 9, 2010Date of Patent: September 25, 2012Assignee: Far East New Century CorporationInventors: Jo-Wei Huang, Mei-Ting Fan Chiang, Ken-Yuan Chang
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Publication number: 20120082837Abstract: A polyglutamic acid (?-PGA) fiber having antibacterial property and high water absorptivity is provided. A main component of the ?-PGA fiber includes a modified ?-PGA, and the modified ?-PGA is a polymer consisting of a ?-glutamic acid segment and a ?-modified glutamic acid segment, in which the modified glutamic acid segment has a formula as shown below: wherein X is H or Na, and Y is Cl, Br or I, and wherein a molar ratio of the modified ?-glutamic acid segment to the ?-glutamic acid segment is not lower than 0.05.Type: ApplicationFiled: March 18, 2011Publication date: April 5, 2012Applicant: FAR EASTERN NEW CENTURY CORPORATIONInventors: Jo-Wei Huang, Chun-Yi Li, Mei-Ting Fan Chiang
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Publication number: 20120051147Abstract: An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines and a second group bit lines; the word line includes a first word line; and the common source lines include a first common source line. In addition, a plurality of sub-memory arrays are provided. Each sub-memory array contains a first, second, third, and fourth memory cells. Wherein, the first and second memory cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged; also, the first and second memory cells, and the third and fourth memory cells are symmetrically arranged with the first common source line as a symmetric axis.Type: ApplicationFiled: August 24, 2010Publication date: March 1, 2012Applicant: YIELD MICROELECTRONICS CORP.Inventors: HSIN-CHANG LIN, CHIA-HAO TAI, YANG-SEN YEN, MING-TSANG YANG, YA-TING FAN
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Publication number: 20120039131Abstract: A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines.Type: ApplicationFiled: August 12, 2010Publication date: February 16, 2012Applicant: YIELD MICROELECTRONICS CORP.Inventors: HSIN-CHANG LIN, CHIA-HAO TAI, YANG-SEN YEN, MING-TSANG YANG, YA-TING FAN
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Publication number: 20120039129Abstract: A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.Type: ApplicationFiled: August 11, 2010Publication date: February 16, 2012Applicant: YIELD MICROELECTRONICS CORP.Inventors: HSIN CHANG LIN, CHIA-HAO TAI, YANG-SEN YEN, MING-TSANG YANG, YA-TING FAN
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Publication number: 20120040504Abstract: The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanting ion into regions of the semiconductor substrate, which are at two sides of the first gate insulation layer, to form two heavily-doped areas that are adjacent to the first gate insulation layer and respectively function as a drain and a source; respectively forming over the first gate layer a second gate insulation layer and a second gate layer functioning as a control gate. The present invention not only increases the transmission speed but also reduces the power consumption, the fabrication cost and the package cost.Type: ApplicationFiled: August 10, 2010Publication date: February 16, 2012Applicant: YIELD MICROELECTRONICS CORP.Inventors: HSIN CHANG LIN, CHIA-HAO TAI, YANG-SEN YEN, MING-TSANG YANG, YA-TING FAN
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Publication number: 20110262523Abstract: The present invention provides a medical adhesive tape comprising a non-woven fabric substrate of a metallocene polypropylene copolymer; and a medical pressure-sensitive adhesive coated on at least one side of said substrate. A medical article comprising a medicament and the medical adhesive tape of the invention is also provided.Type: ApplicationFiled: October 20, 2009Publication date: October 27, 2011Inventors: Dunshen . Zhu, ShiMing Zhou, Ting Fan, Grace L. Ho, Dong Wu
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Patent number: 7905708Abstract: A fan comprises an impeller and a motor. The impeller has a hub, a plurality of blades and a plurality of reinforced elements. The blades are disposed around the hub. At least one reinforced element is disposed on the active surfaces of two adjacent blades. The blades and the reinforced elements are integrally formed as a single piece. The motor connects to the impeller for driving it to rotate.Type: GrantFiled: November 27, 2006Date of Patent: March 15, 2011Assignee: Delta Electronics Inc.Inventors: Jui-Ting Fan, Cheng-Shu Yu, Peng-Chu Tao, Wen-Shi Huang