Abstract: A winged coil structure and a method of manufacturing the same are disclosed. The winged coil structure includes an upper flexible plate, at least one upper magnetic induction coil, at least one upper connection pad, a lower flexible plate, at least one lower magnetic induction coil, at least one lower connection pad, at least one gold finger, a dielectric layer and at least one connection plug. The connection plug connects the upper connection pad and the lower connection pad through thermal pressing such that the gold finger, the upper magnetic induction coil, the upper connection pad, the lower connection pad, the connection plug, the lower connection pad and the lower magnetic induction coil are electrically connected. The upper flexible plate is provided with notched lines to be easily bent without damage to the upper and lower magnetic induction coils. Thus, a bendable feature for magnetic induction coils is provided.

Abstract: Disclosed is a magnetic excitation coil structure including a magnetic coil sheet formed of a thin film and rolled as a cylindrical body with a hollow hole, and an insulation layer covering the outer surface of the cylindrical body formed by the magnetic coil sheet for protection. The magnetic coil sheet includes a flexible substrate, a dielectric layer attached to the flexible substrate, and a plurality of patterned circuit layers embedded in the flexible substrate and in contact with the dielectric layer. Each patterned circuit layer is separate, and the upper surfaces of the patterned circuit layers and the upper surface of the flexible substrate form a co-plane. The magnetic coil structure provides an electrical function of coil, which is enhanced by the patterned circuit layer due to its high aspect ratio of the electrical circuit, thereby greatly increasing the whole magnetic flux and electromagnetic effect.

Abstract: Disclosed is a magnetic excitation coil structure including a magnetic coil sheet formed of a thin film and rolled as a cylindrical body with a hollow hole, and an insulation layer covering the outer surface of the cylindrical body formed by the magnetic coil sheet for protection. The magnetic coil sheet includes a flexible substrate, a dielectric layer attached to the flexible substrate, and a plurality of patterned circuit layers embedded in the flexible substrate and in contact with the dielectric layer. Each patterned circuit layer is separate, and the upper surfaces of the patterned circuit layers and the upper surface of the flexible substrate form a co-plane. The magnetic coil structure provides an electrical function of coil, which is enhanced by the patterned circuit layer due to its high aspect ratio of the electrical circuit, thereby greatly increasing the whole magnetic flux and electromagnetic effect.

Abstract: A method for manufacturing a circuit board with a buried element having high density pin count, wherein a micro copper window formed in a first circuit by patterned dry film electroplating is easily controlled less than 50 ?m so that the micro conduction holes formed after the laser drilling each has a diameter greatly shrunk less than 50 ?m so as to highly increase density of the micro conduction holes, thereby facilitating in burial of the buried element with the high density pin count. Additionally, by disposing the micro conduction holes in the same elevation, optically aligning a fixing position for the buried element can be controlled precisely.

Abstract: Disclosed is a copper etching method for manufacturing a circuit board, including steps of electroplating a metal copper support layer, coating a thermal sensitive photo resist layer, coating a photo resist layer, performing a process of pattern transfer, removing part of the photo resist layer to form a photo resist pattern, electroplating a metal copper layer to form a circuit pattern, peeling off the photo resist layer, pressing a stacked body composed of a stacked substrate and a stacked material layer onto the circuit pattern to embed the circuit pattern in the stacked material layer, removing the base layer, performing a copper etching process to removing the metal copper support layer, and removing the thermal sensitive photo resist layer to expose the circuit pattern. In particular, the circuit pattern protrudes from the stacked material layer so as to facilitate the subsequent process of forming solder balls.

Abstract: A carrier board structure includes at least one upper magnetic coil, at least one lower magnetic coil, a flexible board, a dielectric layer, at least one connection pad and at least one gold finger. The flexible board has a middle region having a middle hole, and two side regions thinner than the middle region. A groove used as a fold line is provided on the lower surface of each side region bordering on the middle region. The upper and lower magnetic coils are configured in the flexible board and separated by the dielectric layer. The gold fingers are provided on the two side regions and connected to the upper magnetic coils. The upper and lower magnetic coils are around the middle hole and connected by the connection pads. The fold lines help the two side regions to fold without damage to the upper and lower magnetic coils.

Abstract: A method for manufacturing a circuit board with a buried element having high density pin count, wherein a micro copper window formed in a first circuit by patterned dry film electroplating is easily controlled less than 50 ?m so that the micro conduction holes formed after the laser drilling each has a diameter greatly shrunk less than 50 ?m so as to highly increase density of the micro conduction holes, thereby facilitating in burial of the buried element with the high density pin count. Additionally, by disposing the micro conduction holes in the same elevation, optically aligning a fixing position for the buried element can be controlled precisely.

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate having a flip region with a through-opening and bonding to a Non-conductive Film to bond to a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with a penetrating rectangular opening bonded to a non-conductive film then a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.

Abstract: An ameliorated compound carrier board structure of Flip-Chip Chip-Scale Package has the insulating layer between the carrier board and the substrate in the prior art replaced by an anisotropic conductive film or materials with similar structure. The anisotropic conductive film has conductive particles therein to replace the conductive openings on the insulating layer in the prior art. When compressing the substrate onto the carrier board, the bottom surface of the second electrode pads are compressing the corresponding conductive particles on the second electrical contact pads, causing which to burst, therefore forming high-density compressed areas that conduct the second electrode pads and the second electrical contact pads; the conductive particles outside the high-density compressed area are not burst, forming an insulating film between the substrate and the carrier board: in other words, the anisotropic conductive film provides conduction in a Z direction.

Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.

Abstract: A method for manufacturing microthrough-hole includes electroplating a metal layer on a carrier plate, patterning the metal layer to form a first circuit having copper pads, covering the first circuit with a photoresist layer and not covering the copper window between two of the copper pads, etching the metal layer beneath the copper window and removing the photoresist layer, sequentially forming an insulation layer and a second circuit on the first circuit and the copper window, the second circuit layer having a stop pad corresponding to the copper window, removing the carrier plate, upward drilling through the insulation layer between the stop pad and the copper window to form a microthrough-hole beneath the stop pad, and forming a conductive layer in the microthrough-hole to form the microthrough-hole connecting the first and second circuits. The microthrough-hole and its occupied area is greatly reduced, thereby achieving high circuit density.

Abstract: A double sided board with buried element and a method for manufacturing the same are disclosed. At least one buried element is fixed on a dielectric layer and embedded in an insulation layer. First and second electrical circuits are formed on upper and lower surfaces of the insulation layer, respectively. At least one through-hole is formed in the insulation layer and filled with a conductive layer to electrically connect the first and the second electrical circuits. The dielectric layer beneath the buried element and the insulation layer above the buried element are provided with at least one opening, respectively, which is filled with the conductive layer, thereby connecting the conductive layer and external circuits or electrical elements. Additionally, the first and second electrical circuits are covered with first and second solder masks, respectively, so as to avoid environmental effect and improve preciseness of the circuits.

Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.

Abstract: A multilayer substrate structure includes a first plastic sheet, a second plastic sheet, a first circuit pattern layer, a second circuit pattern layer, and an interlayer connection pad. A first connection plug connected to the interlayer connection pad fills in a first opening of a first plastic sheet and is connected to a first connection pad of the first circuit pattern layer. A second connection plug fills a second opening of the second plastic sheet and is connected to a second connection pad of the second circuit pattern layer such that the second circuit pattern layer is electrically connected to the first circuit pattern layer via the interlayer connection pad. Therefore, even if there is little offset, it is possible to overcome the alignment tolerance and assure electrical connection between the circuit layers as desired.

Abstract: A stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed.

Abstract: Disclosed is a method of manufacturing a stacked multilayer structure, including the steps of forming a first circuit layer with bumps on a substrate, punching an aluminum plate to form recesses corresponding to the bumps, forming openings in a plastic film including a glass fiber layer corresponding to the bumps, pressing the aluminum plate, the plastic film and the substrate, removing the aluminum plate, polishing to level the resulting surface, forming a second circuit layer connected to the first circuit layer, and finally removing the substrate to form the stacked multilayer structure. Because the glass fiber layer in the plastic film is not exposed after polishing, the thickness of the dielectric layer is uniform and the reliability of the circuit layer is improved so as to increase the yield.

Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate having a flip region with a through-opening and bonding to a Non-conductive Film to bond to a carrier board in order to form a compound carrier board structure. Therefore, when a die is planted in the film region of the carrier board structure, the carrier board is able to susceptible to different stresses during a package process. The baseplate uses the low Thermal Expansion Coefficient material to avoid warpage problems caused by the thermal expansion of the carrier board resulting from the thermal stresses. The carrier board is able to disperse conduction of thermal stresses by the baseplate in order to strengthen cooling effect of the compound carrier board structure. Thus, the present invention achieves miniaturization and heat strengthening and enhances the mechanical strength.

Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.