Patents by Inventor Ting PAN

Ting PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190088937
    Abstract: A novel composite electrode material and a method for manufacturing the same, a composite electrode containing said composite electrode material, and a Li-based battery comprising said composite electrode are disclosed. Herein, the composite electrode material of the present invention comprises: a core, wherein a material of the core is at least one selected from the group consisting of Sn, Sb, Si, Ge, and compounds thereof; and a graphene nanowall or a graphene-like carbon nanowall; wherein the graphene nanowall or the graphene-like carbon nanowall grows on a surface of the core.
    Type: Application
    Filed: December 5, 2017
    Publication date: March 21, 2019
    Inventors: Yon-Hua TZENG, Yen-Ting PAN
  • Publication number: 20190067120
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.
    Type: Application
    Filed: October 4, 2017
    Publication date: February 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHING, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng, Kuan-Ting Pan
  • Patent number: 10196426
    Abstract: A chimeric vector is provided in the present invention, which is formed by ligating a Vif protein and a functional protein, the functional protein being a Raf protein or a Rev protein. By designing and constructing a Rev-Vif-C vector and then demonstrating that the Rev-Vif-C vector has a good anti-virus effect by a variety of experiments, the present invention proposes a novel anti-virus technology against the Rev protein of HIV-1. Moreover, by designing and constructing a RBD-Vif-C vector and then demonstrating that the RBD-Vif-C vector has a good tumor cell killing effect by cell-level experiments in vitro and experiments in vivo with nude mouse tumor models, the present invention proposes a novel anti-tumor technology specifically against mutant KRAS.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: February 5, 2019
    Assignee: SUN YAT-SEN UNIVERSITY
    Inventors: Hui Zhang, Ting Pan
  • Publication number: 20190035912
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes active gate stacks over the fin structure. The semiconductor device structure further includes a dummy gate stack over the fin structure. The dummy gate stack is between the active gate stacks. In addition, the semiconductor device structure includes spacer elements over sidewalls of the dummy gate stack and the active gate stacks. The semiconductor device structure also includes an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements. The isolation feature extends into the fin structure from the bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHING, Shi-Ning JU, Kuan-Ting PAN, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20190035785
    Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.
    Type: Application
    Filed: September 7, 2017
    Publication date: January 31, 2019
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10181426
    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Ting Pan
  • Publication number: 20190006486
    Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Inventors: Kuo-Cheng CHING, Shi-Ning JU, Kuan-Ting PAN, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20180353568
    Abstract: The present invention discloses a use of teicoplanin against Ebola virus, and discloses a drug inhibiting an envelope protein GP that comprises the teicoplanin.
    Type: Application
    Filed: April 22, 2015
    Publication date: December 13, 2018
    Applicant: SUN YAT-SEN UNIVERSITY
    Inventors: Ting PAN, Hui ZHANG, Nan ZHOU
  • Publication number: 20180350969
    Abstract: A semiconductor device is provided, which includes a substrate, a fin structure, a capping layer and an oxide layer. The substrate has a well. The fin structure extends from the well. The capping layer surrounds a top surface and side surfaces of the fin structure. The oxide layer is over the substrate and covers the capping layer. A thickness of a top portion of the oxide layer above the capping layer is greater than a thickness of a sidewall portion of the oxide layer.
    Type: Application
    Filed: June 22, 2017
    Publication date: December 6, 2018
    Inventors: Kuo-Cheng CHING, Kuan-Ting PAN, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 10141419
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. A portion of the semiconductor substrate between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin. A dummy gate electrode is formed to cover a middle portion of the semiconductor fin, with an end portion of the semiconductor fin uncovered by the dummy gate electrode. The dummy gate electrode includes a lower dummy gate electrode portion, and an upper dummy gate electrode portion including polysilicon over the lower dummy gate electrode portion. The lower dummy gate electrode portion and the upper dummy gate electrode portion are formed of different materials. Source/drain regions are formed on opposite sides of the dummy gate electrode. The dummy gate electrode is replaced with a replacement gate electrode.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang, Ying-Keung Leung, Carlos H. Diaz
  • Publication number: 20170345936
    Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.
    Type: Application
    Filed: August 12, 2016
    Publication date: November 30, 2017
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Ching-Wei Tsai, Ying-Keung Leung, Chih-Hao Wang, Carlos H. Diaz
  • Publication number: 20170338326
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. A portion of the semiconductor substrate between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin. A dummy gate electrode is formed to cover a middle portion of the semiconductor fin, with an end portion of the semiconductor fin uncovered by the dummy gate electrode. The dummy gate electrode includes a lower dummy gate electrode portion, and an upper dummy gate electrode portion including polysilicon over the lower dummy gate electrode portion. The lower dummy gate electrode portion and the upper dummy gate electrode portion are formed of different materials. Source/drain regions are formed on opposite sides of the dummy gate electrode. The dummy gate electrode is replaced with a replacement gate electrode.
    Type: Application
    Filed: August 4, 2017
    Publication date: November 23, 2017
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang, Ying-Keung Leung, Carlos H. Diaz
  • Patent number: 9741821
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. A portion of the semiconductor substrate between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin. A dummy gate electrode is formed to cover a middle portion of the semiconductor fin, with an end portion of the semiconductor fin uncovered by the dummy gate electrode. The dummy gate electrode includes a lower dummy gate electrode portion, and an upper dummy gate electrode portion including polysilicon over the lower dummy gate electrode portion. The lower dummy gate electrode portion and the upper dummy gate electrode portion are formed of different materials. Source/drain regions are formed on opposite sides of the dummy gate electrode. The dummy gate electrode is replaced with a replacement gate electrode.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang, Ying-Keung Leung, Carlos H. Diaz
  • Publication number: 20170144670
    Abstract: A vehicle safety method includes steps: monitoring a face state of a driver and determining whether the face state satisfies a tired state or not; sensing a physiological state of the driver and determining whether the physiological state satisfies a conscious state or not; sending a warning query when the face state satisfies the fired state and the physiological state satisfies the conscious state; determining whether a response corresponding to the warning query is received or not; and activating a vehicle safety mechanism if the response corresponding to the warning query is not received.
    Type: Application
    Filed: May 17, 2016
    Publication date: May 25, 2017
    Inventors: Hong-You CHOU, Tai-Yi CHIANG, Po-Tsun YANG, Jeng-Ting PAN
  • Patent number: 9277876
    Abstract: In a method for measuring a metabolic rate of a user, an electronic device is configured to: output a first instruction to instruct the user to pronounce a first specified sound at rest; record a first vocal signal associated with the first specified sound pronounced by the user; output a second instruction to instruct the user to pronounce a second specified sound at exercise; record a second vocal signal associated with the second specified sound pronounced by the user; and evaluate the metabolic rate of the user according to the first vocal signal, the second vocal signal, and a maximum oxygen uptake of the user that is pre-obtained by the electronic device.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: March 8, 2016
    Assignee: SPORT-SUPPORTED CULTURES INTERNATIONAL LTD.
    Inventors: Lu Bi Sha Pu, Chia-Chih Lin, Wen-Kai Tai, Yi-Ting Pan, Jung-Charng Lin
  • Patent number: 8913376
    Abstract: An expandable keyboard device includes a keyboard, and a supporting assembly having interconnected first and second panels. The second panel is adapted to connect with an electronic device. The supporting assembly is movable relative to the keyboard between an unfolded state, where the first panel extends upwardly relative to the keyboard for supporting the electronic device above the keyboard, and a folded state, where the second panel along with the electronic device cover the keyboard. An electrical connector is disposed in the housing for electrical connection with the electronic device. A connecting unit interconnects the supporting assembly and the keyboard.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Wistron Corporation
    Inventors: Wen-Chin Wu, Teng-Yi Chiu, Yen-Ting Pan, Yi-Sheng Kao, Hish-Bin Dai
  • Publication number: 20140296652
    Abstract: In a method for measuring a metabolic rate of a user, an electronic device is configured to: output a first instruction to instruct the user to pronounce a first specified sound at rest; record a first vocal signal associated with the first specified sound pronounced by the user; output a second instruction to instruct the user to pronounce a second specified sound at exercise; record a second vocal signal associated with the second specified sound pronounced by the user; and evaluate the metabolic rate of the user according to the first vocal signal, the second vocal signal, and a maximum oxygen uptake of the user that is pre-obtained by the electronic device.
    Type: Application
    Filed: September 12, 2013
    Publication date: October 2, 2014
    Applicant: Sport-Supported Cultures International Ltd.
    Inventors: Lu Bi SHA PU, Chia-Chih Lin, Wen-Kai Tai, Yi-Ting Pan, Jung-Charng Lin
  • Patent number: 8778602
    Abstract: A method of lithography patterning includes coating a resist layer on a substrate; performing an exposing process to the resist layer using a lithography tool with a numerical aperture tuned between about 0.5 and about 0.6; baking the resist layer; thereafter performing a first developing process to the resist layer for a first period of time; and performing a second developing process to the resist layer for a second period of time.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ting Pan, Jing-Huan Chen, Wei-Chung Ma, Hsin-Chun Chiang, Po-Chung Cheng, Szu-An Wu
  • Patent number: 8654520
    Abstract: A supporting apparatus is used in an electronic apparatus that has a display device, a support base, and a transmission component. The display device is supported by the supporting apparatus and an angle is formed between the display device and the support base. The supporting apparatus includes a first support element, a second support element, a plurality of second axial levers, a first connecting element, and a second connecting element. The first support element is pivotally connected to the display device. The second support element is pivotally connected to the support base. Two ends of the first connecting element are respectively pivotally connected to the first support element and the second support element. Two ends of the second connecting element are respectively pivotally connected to the first support element and the second support element.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: February 18, 2014
    Assignee: Wistron Corporation
    Inventors: Tian-Shyang Lin, Ming-Hua Hung, Shu-Chen Chiang, Wen-Chin Wu, Cheng-Lan Lee, Yen-Ting Pan
  • Publication number: 20130242521
    Abstract: A supporting apparatus is used in an electronic apparatus that has a display device, a support base, and a transmission component. The display device is supported by the supporting apparatus and an angle is formed between the display device and the support base. The supporting apparatus includes a first support element, a second support element, a plurality of second axial levers, a first connecting element, and a second connecting element. The first support element is pivotally connected to the display device. The second support element is pivotally connected to the support base. Two ends of the first connecting element are respectively pivotally connected to the first support element and the second support element. Two ends of the second connecting element are respectively pivotally connected to the first support element and the second support element.
    Type: Application
    Filed: June 28, 2012
    Publication date: September 19, 2013
    Inventors: Tian-Shyang LIN, Ming-Hua Hung, Shu-Chen Chiang, Wen-Chin Wu, Cheng-Lan Lee, Yen-Ting Pan