Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.

Abstract: A method includes forming a first semiconductor layer over a substrate. A second semiconductor layer is formed over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are etched to form a fin structure that extends from the substrate. The fin structure has a remaining portion of first semiconductor layer and a remaining portion of the second semiconductor layer atop the remaining portion of the first semiconductor layer. A capping layer is formed to wrap around three sides of the fin structure. At least a portion of the capping layer and at least a portion of the remaining portion of the second semiconductor layer in the fin structure are oxidized to form an oxide layer wrapping around three sides of the fin structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked wire structure and a second stacked wire structure extending above the isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first stacked wire structure and the second stacked wire structure. The semiconductor device structure also includes a capping layer formed over the dummy fin structure. The isolation structure has a first width, the dummy fin structure has a second width, and the second width is smaller than the first width.

Abstract: The present invention discloses a durable super-hydrophobic manganese dioxide coating and a preparation method thereof, belonging to the field of metallic material surface treatment. In the method, by using manganese sulfate as a raw material, based on the property of interface reaction, a manganese dioxide coating is synthesized on the metallic material surface by simple and convenient solution impregnation, and then processed by hydrophobization with stearic acid to obtain a super-hydrophobic manganese dioxide coating. This coating has excellent chemical stability to organic solvents such as n-hexane, isooctane, dodecane, tetradecane, and acids, alkali and salt solutions at different pH values, and exhibits great resistance against dynamic water shear and good durability, with broad application prospect.

Abstract: A method for forming a FinFET device structure includes forming a first fin structure in a core region of a substrate and a second fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the fin structures. The method also includes forming a dummy oxide layer across the fin structures. The method also includes forming a dummy gate structure over the dummy oxide layer. The method also includes removing the dummy gate structure over fin structures. The method also includes removing the dummy oxide layer and trimming the fin structures. The method also includes forming first and second oxide layers across the first and second fin structures. The method also includes forming first and second gate structures over the first and second oxide layers across the first and second fin structures.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes active gate stacks over the fin structure. The semiconductor device structure further includes a dummy gate stack over the fin structure. The dummy gate stack is between the active gate stacks. In addition, the semiconductor device structure includes spacer elements over sidewalls of the dummy gate stack and the active gate stacks. The semiconductor device structure also includes an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements. The isolation feature extends into the fin structure from the bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure.

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions.

Abstract: A semiconductor device is provided, which includes a substrate, a fin structure, a capping layer and an oxide layer. The substrate has a well. The fin structure extends from the well. The capping layer surrounds a top surface and side surfaces of the fin structure. The oxide layer is over the substrate and covers the capping layer. A thickness of a top portion of the oxide layer above the capping layer is greater than a thickness of a sidewall portion of the oxide layer.

Abstract: A method for forming a FinFET device structure includes forming a first fin structure in a core region of a substrate and a second fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the fin structures. The method also includes forming a dummy oxide layer across the fin structures. The method also includes forming a dummy gate structure over the dummy oxide layer. The method also includes removing the dummy gate structure over fin structures. The method also includes removing the dummy oxide layer and trimming the fin structures. The method also includes forming first and second oxide layers across the first and second fin structures. The method also includes forming first and second gate structures over the first and second oxide layers across the first and second fin structures.

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a second dielectric fin, a semiconductor fin, an epitaxy structure, and a metal gate structure. The first dielectric fin and the second dielectric fin disposed over the substrate. The semiconductor fin is disposed over the substrate, in which the semiconductor fin is between the first dielectric fin and the second dielectric fin. The epitaxy structure covers at least two surfaces of the semiconductor fin, in which the epitaxy structure is in contact with the first dielectric fin and is separated from the second dielectric fin. The metal gate structure crosses the first dielectric fin, the second dielectric fin, and the semiconductor fin.

Abstract: A method for performing adaptive locking range management, an associated data storage device and a controller thereof are provided. The method may include: receiving a security command from outside of the data storage device, wherein the security command is related to changing an old locking range into a new locking range; obtaining a start Logical Block Address (LBA) and a length value of the new locking range according to the security command; determining whether the start LBA of the new locking range is less than an end LBA of the old locking range, and determining whether an end LBA of the new locking range is greater than a start LBA of the old locking range; and in response to both determination results being true, performing data trimming on any respective non-overlapped portions of the new locking range and the old locking range.

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.

Abstract: A chassis includes a bottom plate, a fastener and a supporting component. The bottom plate includes a screw hole. The fastener comprises a threaded portion and a smooth portion that are connected to each other, and the threaded portion is configured to be screwed into the screw hole. The supporting component includes a through hole. The smooth portion of the fastener is configured to be disposed through the through hole so that the supporting component is rotatably disposed on the bottom plate so as to include a supporting position and a stored position. The supporting component is integrated.

Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.

Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.

Abstract: This disclosure relates to a computer case configured to fix an interface card. The computer case includes a main body, a plurality of mount brackets and a framework. The main body includes a first hole and a plurality of second holes. The plurality of second holes are located at a side of the first hole. The plurality of mount brackets are located at the first hole. The framework is conductive. The framework includes a plurality of protrusion portions and a plurality of main portions. The plurality of protrusion portions are connected to the plurality of main portions and are respectively inserted in the plurality of second holes. The framework is disposed on the main body via the plurality of protrusion portions. The plurality of main portions are respectively in contact with the plurality of mount brackets.

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions.

Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.