Patents by Inventor Ting PAN
Ting PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230246028Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures stacked in a vertical direction over a substrate, and a first dummy fin structure between the first nanostructures and the second nanostructures. The semiconductor device structure includes a first gate structure formed over the first nanostructures, wherein the first gate structure includes a gate dielectric layer, and the gate dielectric layer is in direct contact with a sidewall surface of the first dummy fin structure.Type: ApplicationFiled: April 7, 2023Publication date: August 3, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng CHIANG, Shi-Ning JU, Chih-Hao WANG, Kuan-Ting PAN, Zhi-Chang LIN
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Publication number: 20230223305Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Ting Pan, Chih-Hao Wang, Kuo-Cheng Chiang, Yi-Bo Liao, Yi-Ruei Jhan
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Patent number: 11688809Abstract: A semiconductor device structure includes a fin structure, a semiconductive capping layer, an oxide layer, and a gate structure. The fin structure protrudes above a substrate. The semiconductive capping layer wraps around three sides of a channel region of the fin structure. The oxide layer wraps around three sides of the semiconductive capping layer. A thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer. The gate structure wraps around three sides of the oxide layer.Type: GrantFiled: April 17, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230197850Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Pei-Yu WANG, Cheng-Ting CHUNG, Chih-Hao WANG
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Patent number: 11681336Abstract: A removable adhesive member and a display device using the same is provided. The removable adhesive member includes a first adhesive section, a first connecting section, and a tearing portion. The two opposite surfaces of the first adhesive section respectively adhere to the two objects. The first connecting section is connected to the first adhesive section. The first connecting section includes a first adhesive layer and two first protective layers. One side of the first adhesive section extends to form the first adhesive layer. The first protective layers are respectively laminated to two opposite surfaces of the first adhesive layer. The tearing portion is connected to the first adhesive section through the first connecting section, thereby avoiding rupture in pulling the tearing portion. The tearing portion is conveniently pulled up by a user, such that the first adhesive section removes from the objects to disassemble the objects.Type: GrantFiled: July 14, 2021Date of Patent: June 20, 2023Assignees: Interface Technology (Chengdu) Co., Ltd, Interface Optoelectronics (Shenzhen) Co., Ltd., Interface Optoelectronics (Wu xi) Co., Ltd, General Interface Solution LimitedInventors: Chun Ting Pan, Feng Chun Hsieh, Yi Hsin Lin
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Patent number: 11676864Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.Type: GrantFiled: August 27, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shi-Ning Ju, Shang-Wen Chang, Chih-Hao Wang
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Publication number: 20230178555Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.Type: ApplicationFiled: January 30, 2023Publication date: June 8, 2023Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi-Ning JU, Yi-Ruei JHAN, Kuan-Lun CHENG, Chih-Hao WANG
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Publication number: 20230155003Abstract: A semiconductor device structure includes a fin structure over a semiconductor substrate and a dummy gate stack formed over the fin structure and having a first sidewall and an opposite second sidewall. The semiconductor device structure also includes a first and second source or drain (S/D) structures in the fin structure and respectively adjacent to the first and second sidewalls of the dummy gate stack. The semiconductor device structure further includes an isolation feature formed in the fin structure below the dummy gate stack and having a third sidewall and an opposite fourth sidewall. A first end of the third sidewall overlaps the first end of the fourth sidewall. A second end of the third sidewall is in direct contact with a bottom of the dummy gate stack. A second end of the fourth sidewall is separated from the bottom of the dummy gate stack.Type: ApplicationFiled: January 20, 2023Publication date: May 18, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng CHING, Shi-Ning JU, Kuan-Ting PAN, Kuan-Lun CHENG, Chih-Hao WANG
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Patent number: 11637102Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.Type: GrantFiled: March 12, 2021Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
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Publication number: 20230124914Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: Kuan-Ting Pan, Kuo-Cheng CHIANG, Shi Ning JU, Yi-Ruei Jhan, KUAN-LUN CHENG, CHIH-HAO WANG
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Patent number: 11626509Abstract: A semiconductor device includes a substrate, a first dielectric fin, a semiconductor fin, a metal gate structure, an epitaxy structure, and a contact etch stop layer. The first dielectric fin is disposed over the substrate. The semiconductor fin is disposed over the substrate, in which along a lengthwise direction of the first dielectric fin and the semiconductor fin, the first dielectric fin is in contact with a first sidewall of the semiconductor fin. The metal gate structure crosses the first dielectric fin and the semiconductor fin. The epitaxy structure is over and in contact with the semiconductor fin. The contact etch stop layer is over and in contact with first dielectric fin.Type: GrantFiled: May 7, 2021Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11626402Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked structure and a second stacked structure extending above the isolation structure. The first stacked structure includes a plurality of first nanostructures stacked in a vertical direction, and the second stacked structure includes a plurality of second nanostructures stacked in the vertical direction. The semiconductor device structure includes a first dummy fin structure formed over the isolation structure, and the first dummy fin structure is between the first stacked structure and the second stacked structure. The semiconductor device structure also includes a first capping layer formed over the first dummy fin structure, and an interface between the first dummy fin structure and the first capping layer is lower than a top surface of a topmost first nanostructure.Type: GrantFiled: December 22, 2021Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin
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Patent number: 11621195Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.Type: GrantFiled: April 23, 2020Date of Patent: April 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Ting Pan, Chih-Hao Wang, Kuo-Cheng Chiang, Yi-Bo Liao, Yi-Ruei Jhan
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Patent number: 11616062Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.Type: GrantFiled: February 8, 2021Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Ting Pan, Zhi-Chang Lin, Chih-Hao Wang, Shih-Cheng Chen
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Publication number: 20230060454Abstract: A device includes a substrate and a fin isolation structure between a first gate structure and a second gate structure. The first gate structure wraps around a first vertical stack of nanostructure channels overlying a first fin. The second gate structure wraps around a second vertical stack of nanostructure channels overlying a second fin. The fin isolation structure extends from an upper surface of the first gate structure to an upper surface of the substrate. A trench isolation structure is between the first fin and the fin isolation structure, and has different etch selectivity than the fin isolation structure.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Yi-Ruei JHAN, Kuan-Ting PAN, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20230053451Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.Type: ApplicationFiled: November 4, 2022Publication date: February 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng CHING, Zhi-Chang LIN, Kuan-Ting PAN, Chih-Hao WANG, Shi-Ning JU
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Patent number: 11581437Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.Type: GrantFiled: March 11, 2021Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Pei-Yu Wang, Cheng-Ting Chung, Chih-Hao Wang
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Publication number: 20230045491Abstract: A semiconductor device includes an active area extending in a first direction over a substrate, the active area including at least one conductive path extending from a source region, through a channel region, to a drain region; and a gate dielectric on a surface of the at least one conductive path in the channel region. The semiconductor device also includes an isolating fin at a first side of the active area, the isolating fin having a first fin region having a first fin width adjacent to the source region, a second fin region having a second fin width adjacent to the channel region, and a third fin region having the first fin width adjacent to the drain region; and a gate electrode against the gate dielectric in the channel region.Type: ApplicationFiled: August 5, 2021Publication date: February 9, 2023Inventors: Jia-Chuan YOU, Kuan-Ting PAN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 11569234Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.Type: GrantFiled: September 21, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shi-Ning Ju, Yi-Ruei Jhan, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11563106Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.Type: GrantFiled: April 27, 2020Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang