Abstract: A contact lens material includes: a hydrophilic monomer, a crosslinking agent, an initiator, and a siloxane monomer. Based on a total weight of the contact lens material being 100 parts by weight, an amount of the siloxane monomer is between 5 parts by weight and 50 parts by weight. A chemical empirical formula of the siloxane monomer is: CaHbOcNdSie, in which C represents carbon atoms, a is a positive number between 12 and 55, H represents hydrogen atoms, b is a positive number between 29 and 121, O represents oxygen atoms, c is a positive number between 4 and 17, N represents nitrogen atoms, d is a positive number between 0 and 5, Si represents silicon atoms, and e is a positive number between 1 and 9.

Abstract: The present disclosure includes a voltage provision circuit. In one aspect of the present disclosure, a voltage provision circuit is disclosed. The voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage. The voltage provision circuit includes a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage. The voltage provision circuit includes a first PMOS transistor sourced with a first supply voltage. The voltage provision circuit includes a second PMOS transistor sourced with the first supply voltage. The voltage provision circuit includes a voltage modulation circuit, coupled between the first to second PMOS transistors and the first to second NMOS transistors, that is configured to provide a first intermediate signal based on the first and second control signals.

Abstract: Disclosed in the present invention are a dynamic maximal clique enumeration device and method based on an FPGA with an HBM, the method including: the HBM stores a dynamic edge flow, a complete graph adjacency matrix, and candidate cliques; a matrix computing unit updates the complete graph adjacency matrix based on the dynamic edge flow, transmits the updated complete graph adjacency matrix to the HBM for storage, and determines header nodes, of which the corresponding candidate clique needs to be updated; a sequence computing unit constructs, according to the updated complete graph adjacency matrix and each header node to be updated, the sorted data set for reconstructing candidate cliques by data block sequencing; and an update computing unit executes, in parallel, an update task of the candidate clique corresponding to each header node to be updated based on the sorted data set, transmits the updated candidate cliques to the HBM for storage, and transmits the updated candidate cliques to the PC host to ext

Abstract: Disclosed are a cement-based battery and a method for manufacturing thereof. The cement-based battery includes a waterproof structure, a battery body, a positive electrode, a negative electrode, and an electrolyte solution. The waterproof structure is provided with an accommodating cavity. The battery body is disposed in the accommodating cavity, and includes a cement-based body, which is obtained by curing a solid-liquid mixture, wherein the solid-liquid mixture includes cement, a first porous material, and a first effective microorganism aqueous solution. The positive electrode and the negative electrode are connected to the battery body respectively and extend out of the waterproof structure. The electrolyte solution is disposed in the accommodating cavity. Therefore, the cement-based battery can be applied to a cement building as an energy storage battery to provide power at night, during power outages or during emergencies.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a front-side interconnect structure formed over a front side of a base layer and a back-side interconnect structure formed over a back side of a base layer. The front-side interconnect structure includes at least one passive element and the back-side interconnect structure includes at least one passive element. The passive element is selected from a capacitor, an inductor and a combination thereof.

Abstract: The present invention disclose methods for increasing chromium in white kidney bean. The method comprises preparing field, performing a first treatment to the seeds of the white kidney bean, performing a second treatment during the seeding period, performing a third treatment during the flowering period, performing a forth treatment during the fruiting period and performing a fifth treatment during the maturing period. Meanwhile, the amount of chromium in the white kidney bean produced according to the present invention is approximately from 400 to 800 mg/kg.

Abstract: A gas cooling module for an immersion electronic apparatus and a test device equipped with the gas cooling module are provided. The immersion electronic apparatus includes a boiler disposed on a heat source of a circuit board. The gas cooling module includes a gas supply source and a fluid guide member. Cooling gas is introduced from the gas supply source into the fluid guide member, and is ejected toward the boiler, so that heat can be effectively taken away, and the immersion electronic apparatus can be tested in an air environment. The test device further integrates a housing, the immersion electronic apparatus is placed in the housing, and the test device is equipped with the foregoing gas cooling module, to perform a more comprehensive performance test.

Abstract: A method includes processing, by one or more processors, historical claim and claim remittance information to extract prior authorization data; performing, by the one or more processors, a probabilistic analysis on the prior authorization data for a procedure to generate a first metric and a second metric, the first metric comprising a percentage of claims including the procedure in which prior authorization is applied for and the second metric comprising a percentage of claims including the procedure in which prior authorization was not applied for and were denied payment for not applying for prior authorization; determining, by the one or more processors, whether the first metric satisfies a first authorization threshold and the second metric satisfies a second authorization threshold, the first and second thresholds being associated with a prior authorization rule corresponding to the procedure; and generating, by the one or more processors, a recommendation on whether to obtain prior authorization before

Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes an N-type deep well region (DNW), first and second high-voltage P- and N-type well regions (first and second HVPW and HVNW), a low-voltage N-type well region (LVNW), first and second P- and first N-type doped regions in a P-type semiconductor substrate, and a gate structure. The first and second HVPW and HVNW are located on the DNW. The LVNW is located on the first HVPW. The first P- and N-type doped regions and second P-type doped region are located on the LVNW and the second HVNW and HVPW. The first P-type doped region is electrically connected to a first voltage source. The gate structure on the first and second HVPW and the first HVNW, the second P-type doped region and the first N-type doped region are electrically connected to a second voltage source.

Abstract: A semiconductor device includes a substrate, an upper layer disposed over the substrate and comprises an upper electrical pattern and an alignment mark pattern electrically insulated from the upper electrical pattern, and a lower layer disposed between the substrate and the upper layer and including a lower electrical pattern and a dummy pattern electrically insulated from the lower electrical pattern, wherein the alignment mark pattern overlaps the dummy pattern from a top view, the alignment mark pattern has an optical contrast in relation to the dummy pattern, and the optical contrast is substantially equal to or greater than 50.

Abstract: An ESD protection device includes a substrate, an epitaxial layer, first to third well regions, and first to sixth doped regions. The first to third well regions are disposed in the epitaxial layer. The third well region is disposed between the first and second well regions. The first and second doped regions are disposed on the first well region and coupled to a pad. The third and fourth doped regions are disposed on the second well region and coupled to a ground terminal. The fifth doped region is disposed on the third well region, and the sixth doped region is disposed in the fifth doped region. The third, fifth, and sixth doped regions have the same conductive type. In response to an electrostatic discharge event occurring on the pad, a discharge path is formed between the pad and the ground terminal.

Abstract: A laser soldering method using dynamic light spot is provided and includes following steps: executing a soldering to control a laser module to radiate toward multi-lens to form a light spot on a soldering target; and, adjusting a lens distance between the multi-lens based on a spot-adjustment condition to adjust a light spot size of the light spot when the spot-adjustment condition is met in the soldering. The disclosure may provide multiple heating densities respectively adequate to different soldering status via adjusting the light spot size when using same laser power, so as to improve the soldering quality.

Abstract: An exemplary work press assembly for a test handler includes a presser and a guide frame. The presser is configured to secure a device under test (DUT) and press the DUT into a socket for testing. The guide frame is configured to receive guide pins of the socket. The presser extends through an opening of the guide frame, and the guide frame is sandwiched between a first presser portion and a second presser portion. The presser is formed of a first material having a first coefficient of thermal expansion (CTE), and the guide frame is formed from a second material having a second CTE that is less than the first CTE. In some embodiments, a thermal insulation layer(s) separates the presser from the guide frame. In some embodiments, a spacing between sidewalls of the presser and sidewalls of the guide frame is configured to accommodate thermal expansion of the presser.

Abstract: A package shuttle includes a lower shuttle assembly including a first lower shuttle structural element, an array of conductive plates located over the first lower shuttle structural element, and at least one second lower shuttle structural element including an array of shuttle openings therethrough. The array of shuttle openings overlies the array of conductive plates and is configured to accommodate an array of semiconductor packages therein. The package shuttle may further include an upper shuttle assembly including an carrier substrate and an array of package clamps attached to a bottom surface of the carrier substrate. The array of package clamps is configured to mate with the lower shuttle assembly such that the lower shuttle assembly is secure against lateral movement relative to the upper shuttle assembly upon mating of the lower shuttle assembly with the upper shuttle assembly.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Abstract: The present disclosure relates to an automated tool for STIX report generation from threat intelligence text. In a second aspect of the present disclosure, a method of using an automated tool for STIX report generation from threat intelligence text.

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Abstract: A filler cell region (in a semiconductor device) includes: filler-gate segments; for which a majority of first ends substantially align with a first reference line and a majority of second ends substantially align with a second reference line, the first and second reference lines being parallel and proximal to a top and bottom boundaries of the filler cell region; first and second filler-gate segments extending continuously across the filler cell region; and third & fourth and fifth & sixth filler-gate segments being correspondingly coaxial and separated by corresponding gate-gaps located centrally in the filler cell region; the first and second filler-gate segments being between the third & fourth filler-gate segments and the fifth & sixth filler-gate segments; and a first end of the first or second filler-gate segment extending to the top boundary; and a second end of the first or second filler-gate segment extending to the bottom boundary.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. A plurality of conductive balls is placed over a circuit substrate, where each of the conductive balls is placed over a contact area of one of a plurality of contact pads that is accessibly revealed by a patterned mask layer. The conductive balls are reflowed to form a plurality of external terminals with varying heights connected to the contact pads of the circuit substrate, where a first external terminal of the external terminals formed in a first region of the circuit substrate and a second external terminal of the external terminals formed in a second region of the circuit substrate are non-coplanar.

Abstract: An integrated circuit includes a first active region, a first contact, a first and second conductor and a first and second via. The first active region extends in a first direction, and is on a first level of a substrate. The first contact extends in a second direction, is on a second level, and overlaps the first active region. The first conductor extends in the first direction, overlaps the first contact, and is on a third level. The second conductor extends in the first direction, is on the third level, overlaps the first contact, and is separated from the first conductor in the second direction. The first via is between the first contact and first conductor, and electrically couples the first contact and the first conductor together. The second via is between the first contact and the second conductor, and electrically couples the first contact and the second conductor together.