Patents by Inventor To-Nien Lin
To-Nien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190378927Abstract: A semiconductor device includes a substrate, a gate disposed over the substrate, a source/drain disposed in the substrate at two sides of the gate, and an insulating layer disposed over sidewalls of the gate and at least a portion of a surface of the source/drain. In some embodiments, the insulating layer includes a first side facing the gate or the source, and includes a second side opposite to the first side. The insulating layer includes dopants, and a concentration of the dopants is reduced from the second side to the first side of the insulating layer.Type: ApplicationFiled: June 12, 2018Publication date: December 12, 2019Inventors: HONG-NIEN LIN, MING-HENG TSAI, YONG-YAN LU, CHUN-SHENG LIANG, JENG-YA YEH
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Publication number: 20190271804Abstract: A projection device includes a laser source and a birefringent depolarizer. The birefringent depolarizer is a single wedge shape and is arranged in front of a projection lens. The laser source is configured to emit a laser beam to penetrate the birefringent depolarizer to be a projection beam having multiple polarization patterns different from polarization patterns of the laser beam. The projection beam is projected onto a projection screen through the projection lens. The polarization patterns are multiple different polarization directions.Type: ApplicationFiled: September 18, 2018Publication date: September 5, 2019Inventors: Yu-Nien LIN, Meng-Han LIU
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Publication number: 20180350800Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.Type: ApplicationFiled: July 30, 2018Publication date: December 6, 2018Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling-Yen YEH, Wilman TSAI, Yee-Chia YEO
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Publication number: 20180151745Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.Type: ApplicationFiled: March 31, 2017Publication date: May 31, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling-Yen YEH, Wilman TSAI, Yee-Chia YEO
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Patent number: 9653552Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: July 8, 2016Date of Patent: May 16, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 9577370Abstract: A high-speed electrical connector includes an insulating case, several signal terminals, several grounding terminals, an electrical bridge, and several resilient conductive buffers mounted in the insulating case. Each of the signal and grounding terminals has a fixing segment and a swing segment swingable with respect to the fixing segment. The electrical bridge corresponds to two of the grounding terminals. The conductive buffers are disposed on the electrical bridge and are respectively arranged in the swing paths of the swing segments. Each conductive buffer is configured to transform from an initial state to a deformation state by pressing. Each swing segment can swing to press the corresponding conductive buffer, causing the corresponding conductive buffer to be in the deformation state, thereby establishing an electrical connection path between the electrical bridge and the corresponding grounding terminals. In one example, the buffer can be formed of elastomer mixed with conductive particles.Type: GrantFiled: October 16, 2015Date of Patent: February 21, 2017Assignee: GREENCONN CORP.Inventors: Han-Nien Lin, Tung-Chi Hsieh, Keh-Chang Cheng
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Publication number: 20160344134Abstract: A high-speed electrical connector includes an insulating case, several signal terminals, several grounding terminals, at least one electrical bridge, and several resilient conductive buffers, which are mounted in the insulating case. Each one of the signal and grounding terminals has a fixing segment and a swing segment swingable with respect to the fixing segment. The electrical bridge corresponds to at least two of the grounding terminals. The conductive buffers are disposed on the electrical bridge and are respectively arranged in the swing paths of the swing segments of the grounding terminals. Each conductive buffer is configured to transform from an initial state to a deformation state by pressing. Each swing segment can swing to press the corresponding conductive buffer, causing the corresponding conductive buffer to be in the deformation state, thereby establishing an electrical connection path between the electrical bridge and the corresponding grounding terminals.Type: ApplicationFiled: October 16, 2015Publication date: November 24, 2016Inventors: HAN-NIEN LIN, TUNG-CHI HSIEH, KEH-CHANG CHENG
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Publication number: 20160322463Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: July 8, 2016Publication date: November 3, 2016Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 9419786Abstract: A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.Type: GrantFiled: March 27, 2015Date of Patent: August 16, 2016Assignee: MStar Semiconductor, Inc.Inventors: Po-Nien Lin, Meng-Tse Weng, Jiunn-Yih Lee
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Patent number: 9406800Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: December 15, 2015Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Publication number: 20160104800Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: December 15, 2015Publication date: April 14, 2016Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 9285642Abstract: A pixel array includes pixel units. A gate of a sharing switch device is electrically connected to a signal line. A source of the sharing switch device is electrically connected to an active device and a sub-pixel electrode. A terminal of a first capacitance Cpp is electrically connected to the source of the sharing switch device and the sub-pixel electrode. Another terminal of the first capacitance Cpp is electrically connected to a main pixel electrode of the next pixel unit. A terminal of a second capacitance Ccc is electrically connected to a drain of the sharing switch device. Another terminal of the second capacitance Ccc is electrically connected to the main pixel electrode of the next pixel unit. 5%?(Ccc/Cpp)?25%.Type: GrantFiled: February 3, 2015Date of Patent: March 15, 2016Assignee: Au Optronics CorporationInventors: Po-Nien Lin, Yu-Ching Wu, Tien-Lun Ting
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Patent number: 9276592Abstract: A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.Type: GrantFiled: December 24, 2014Date of Patent: March 1, 2016Assignee: MStar Semiconductor, Inc.Inventors: Po-Nien Lin, Jiunn-Yih Lee
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Publication number: 20160033833Abstract: A pixel array includes pixel units. A gate of a sharing switch device is electrically connected to a signal line. A source of the sharing switch device is electrically connected to an active device and a sub-pixel electrode. A terminal of a first capacitance Cpp is electrically connected to the source of the sharing switch device and the sub-pixel electrode. Another terminal of the first capacitance Cpp is electrically connected to a main pixel electrode of the next pixel unit. A terminal of a second capacitance Ccc is electrically connected to a drain of the sharing switch device. Another terminal of the second capacitance Ccc is electrically connected to the main pixel electrode of the next pixel unit. 5%?(Ccc/Cpp)?25%.Type: ApplicationFiled: February 3, 2015Publication date: February 4, 2016Inventors: Po-Nien Lin, Yu-Ching Wu, Tien-Lun Ting
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Patent number: 9214554Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: January 28, 2015Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 9166847Abstract: A signal receiving apparatus includes an equalization module, a coarse tuning module and a fine tuning module. The equalization module receives an input signal, and performs an equalization process on the input signal according to an equalization strength to generate an equalized signal. The coarse tuning module adjusts the equalization strength according to the equalized signal until the equalized signal satisfies a preliminary convergence condition. When the preliminary convergence condition is satisfied, the fine tuning module adjusts the equalization strength according to the equalized signal until the equalization strength satisfies a final convergence condition.Type: GrantFiled: January 15, 2015Date of Patent: October 20, 2015Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Po-Nien Lin, Jyun-Yang Shih, Jiunn-Yih Lee
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Publication number: 20150280761Abstract: A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.Type: ApplicationFiled: March 27, 2015Publication date: October 1, 2015Inventors: Po-Nien Lin, Meng-Tse Weng, Jiunn-Yih Lee
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Publication number: 20150207652Abstract: A signal receiving apparatus includes an equalization module, a coarse tuning module and a fine tuning module. The equalization module receives an input signal, and performs an equalization process on the input signal according to an equalization strength to generate an equalized signal. The coarse tuning module adjusts the equalization strength according to the equalized signal until the equalized signal satisfies a preliminary convergence condition. When the preliminary convergence condition is satisfied, the fine tuning module adjusts the equalization strength according to the equalized signal until the equalization strength satisfies a final convergence condition.Type: ApplicationFiled: January 15, 2015Publication date: July 23, 2015Inventors: Po-Nien Lin, Jyun-Yang Shih, Jiunn-Yih Lee
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Publication number: 20150206970Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: January 28, 2015Publication date: July 23, 2015Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang-Yu
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Publication number: 20150188697Abstract: A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.Type: ApplicationFiled: December 24, 2014Publication date: July 2, 2015Inventors: Po-Nien Lin, Jiunn-Yih Lee