Patents by Inventor Tobias Werner

Tobias Werner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250013811
    Abstract: Embodiments of the present disclosure provide systems and methods for efficiently performing device changes directly in an extracted netlist, without requiring independent changes in a schematic design or layout view of the IC design. A disclosed method accesses a netlist for a selected device in a given integrated circuit (IC) design; and identifies a change to be made in the netlist. The system performs, based on the selected change to the netlist, at least one of changing one or multiple parameters of the selected device; adding a second selected device; removing the selected device, or changing an interconnect. The system can implement changes to the netlist using batch processing.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Inventors: Itay ISRAELI, Israel A. WAGNER, Tobias WERNER, Tai Anh CAO, Hed KONEN, Avital RAFAEVICH
  • Patent number: 12136916
    Abstract: The invention relates to an operator control unit for a measuring instrument for process or automation engineering, the operator control unit consisting of at least two adjacently arranged control panels (10a), the control panels (10a) being operated by pressing on a respective shape-variable or elastic housing region (2a) having a respective capacitive sensor element (11) disposed thereunder. The sensor elements (11) each have a first electrode (11a) as a lower plate capacitor and a counter-electrode (11b) arranged in parallel thereabove as an upper plate capacitor, and pressing on one of the housing regions (2a) causes the respective upper plate capacitor (11b) to approach the respective lower plate capacitor (11a), thus changing the capacitance. The first electrode (11a) is attached to a first carrier material (12) and the counter-electrode (11b) is attached to a second carrier material (13).
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 5, 2024
    Assignee: IFM Electronic GmbH
    Inventors: Christian Kreisel, Patrick Werner, Walter Reichart, Tobias May
  • Publication number: 20240308001
    Abstract: An apparatus for additively manufacturing three-dimensional objects may include at least one calibration unit, at least one irradiation device, and a determination device. The least one calibration unit may include at least one calibration region arranged in the beam guiding plane, and the at least one calibration region may include a plurality of sub-regions differing in respect of at least one optical property. The at least one irradiation device may be configured to guide a plurality of energy beams across the at least one calibration region comprising the plurality of sub-regions, and a plurality of calibration signals may be generated by the plurality of sub-regions being irradiated with the plurality of energy beams. The determination device may be configured to determine the plurality of calibration signals and to determine a calibration status of the irradiation device based at least in part on the determined plurality of calibration signals.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Juergen Werner, Dominic Graf, Jonathan William Ortner, Lisa Pastuschka, Tobias Bokkes
  • Publication number: 20240298524
    Abstract: The present invention relates to an electrically doped semiconducting material comprising at least one metallic element as n-dopant and at least one electron transport matrix compound comprising at least one phosphine oxide group, a process for its preparation, and an electronic device comprising the electrically doped semiconducting material.
    Type: Application
    Filed: April 10, 2024
    Publication date: September 5, 2024
    Inventors: Omrane Fadhel, Carsten Rothe, Jan Birnstock, Ansgar Werner, Kai Gilge, Jens Angermann, Mike Zöllner, Francisco Bloom, Thomas Rosenow, Tobias Canzler, Tomas Kalisz, Ulrich Denker
  • Publication number: 20240121934
    Abstract: A processor may form a first power line and a second power line. The processor may form a first memory cell with at least six transistors and a second memory cell with at least six transistors. The first pair of transistors of the first memory cell may be stacked vertically and connected at a common net. The common net may be arranged transverse to the first pair of transistors. The first pair of transistors may be configured to share the first power line. The second pair of transistors of the first memory cell may be stacked vertically and connected at a common net. The common net may be arranged transverse to the second pair of transistors. The second pair of transistors may be configured to share the second power line. The transistors of the first pair of transistors are configured to operate independently from the second pair of transistors.
    Type: Application
    Filed: December 22, 2022
    Publication date: April 11, 2024
    Inventors: Jens Künzer, Tobias Werner, Iris Maria Leefken, Gerhard Hellner
  • Patent number: 11467078
    Abstract: A particle sensor is described. The particle sensor includes a laser module having a laser, and a detector configured to detect thermal radiation. The particle sensor has an optical apparatus that is configured to focus laser light proceeding from the laser module into a first spot and is configured to focus thermal radiation proceeding from the first spot into a second spot, a radiation-sensitive surface of the detector being located in the second spot, or behind the second spot in the beam path of the thermal radiation focused onto the second spot.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 11, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Jens Ehlermann, Matthias Wichmann, Radoslav Rusanov, Tobias Werner
  • Patent number: 11328110
    Abstract: An integrated circuit includes at least one first area including logic circuitry. The logic circuitry includes library blocks selected from a logic circuit library. A first one of the library blocks is provided with at least two symmetry mirror edges perpendicular to a height of the library blocks. Two adjacent ones of the library blocks are joined at a common symmetry mirror edge.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: May 10, 2022
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Tobias Werner, Shankar Kalyanasundaram, Rolf Sautter
  • Patent number: 11171142
    Abstract: An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
  • Patent number: 11164879
    Abstract: An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
  • Publication number: 20210312116
    Abstract: An integrated circuit includes at least one first area including logic circuitry. The logic circuitry includes library blocks selected from a logic circuit library. A first one of the library blocks is provided with at least two symmetry mirror edges perpendicular to a height of the library blocks. Two adjacent ones of the library blocks are joined at a common symmetry mirror edge.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 7, 2021
    Inventors: Juergen Pille, Tobias Werner, Shankar Kalyanasundaram, Rolf Sautter
  • Publication number: 20200371009
    Abstract: A particle sensor is described. The particle sensor includes a laser module having a laser, and a detector configured to detect thermal radiation. The particle sensor has an optical apparatus that is configured to focus laser light proceeding from the laser module into a first spot and is configured to focus thermal radiation proceeding from the first spot into a second spot, a radiation-sensitive surface of the detector being located in the second spot, or behind the second spot in the beam path of the thermal radiation focused onto the second spot.
    Type: Application
    Filed: February 15, 2019
    Publication date: November 26, 2020
    Inventors: Jens Ehlermann, Matthias Wichmann, Radoslav Rusanov, Tobias Werner
  • Patent number: 10833089
    Abstract: An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
  • Patent number: 10804266
    Abstract: An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
  • Patent number: 10712568
    Abstract: A projection apparatus for data eyeglasses. The projection apparatus encompasses at least one light source for emitting a light beam; and at least one holographic element, disposed or disposable on an eyeglass lens of the data eyeglasses, for projecting an image onto a retina of a user of the data eyeglasses by deflecting and/or focusing the light beam onto a eye lens of the user.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 14, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Reinhold Fiess, Tobias Werner
  • Publication number: 20200161312
    Abstract: An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Juergen PILLE, Albert FRISCH, Tobias WERNER, Rolf SAUTTER, Dieter WENDEL
  • Publication number: 20200161300
    Abstract: An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Juergen PILLE, Albert FRISCH, Tobias WERNER, Rolf SAUTTER, Dieter WENDEL
  • Publication number: 20200161311
    Abstract: An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Juergen PILLE, Albert FRISCH, Tobias WERNER, Rolf SAUTTER, Dieter WENDEL
  • Publication number: 20200161310
    Abstract: An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Juergen PILLE, Albert FRISCH, Tobias WERNER, Rolf SAUTTER, Dieter WENDEL
  • Publication number: 20190221327
    Abstract: One aspect relates to a piezoresistive material, a detection unit having such piezoresistive material, and a method for producing such piezoresistive material. Further, several uses of the material uses of the piezoresistive material or the detection unit are described. The piezoresistive material includes a compound of a carbon component and an elastomer component. The carbon component includes carbon particles including macropores. The elastomer component includes polymeric chains. At least some of the macropores in the carbon particles are infiltrated by polymeric chains to form a piezoresistive interconnection between the carbon particles.
    Type: Application
    Filed: September 11, 2017
    Publication date: July 18, 2019
    Applicant: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Stefan SCHIBLI, Heiko SPECHT, Christian NEUMANN, Tobias WERNER
  • Publication number: 20180203234
    Abstract: A projection apparatus for data eyeglasses. The projection apparatus encompasses at least one light source for emitting a light beam; and at least one holographic element, disposed or disposable on an eyeglass lens of the data eyeglasses, for projecting an image onto a retina of a user of the data eyeglasses by deflecting and/or focusing the light beam onto a eye lens of the user.
    Type: Application
    Filed: June 13, 2016
    Publication date: July 19, 2018
    Inventors: Reinhold Fiess, Tobias Werner