Abstract: An SRAM array having multiple cell cores to store and retrieve data. A cell core includes a plurality of SRAM cells, and at least two corresponding cell cores build a cell core row. A word decoder is configured to decode incoming address signals. The word decoder includes a cell core select unit configured to generate a cell core row select signal from a combination of a first part of the incoming address signals and a received clock signal.

Abstract: An SRAM array having multiple cell cores to store and retrieve data. A cell core includes a plurality of SRAM cells, and at least two corresponding cell cores build a cell core row. A word decoder is configured to decode incoming address signals. The word decoder includes a cell core select unit configured to generate a cell core row select signal from a combination of a first part of the incoming address signals and a received clock signal.

Abstract: The invention relates to a method for operating an electrical machine (1) controlled by an inverter (2), wherein the inverter (2) comprises half-bridge branches (10-U, 10-V, 10-W) having power components in the form of controllable power switching elements (3) and power diodes (4) respectively connected in parallel therewith, wherein each of the half-bridge branches (10-U; 10-V; 10-W) is arranged on a separate semiconductor module (11-U; 11-V; 11-W), which are arranged jointly on a baseplate (12), wherein the phase currents (1_U, 1_V, 1_W) flowing through the half-bridge branches (10-U, 10-V, 10-W), the voltages present at the power components and temperatures (t_Sens_U, t_Sens_V, t_Sens_W) on the semiconductor modules (11-U, 11-V, 11-W) are determined, from the current (1_U; 1_V; 1_W) respectively flowing at a power component and from the voltage respectively present a power loss (P) is calculated for each of the power components, from the power losses (P) a relevant temperature swing (?t; ?t_Sens) is determ

Abstract: Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.

Abstract: A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data.

Abstract: A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The second switch is configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal. The third switch is configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal. The fourth switch is configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal.

Abstract: Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.

Abstract: A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data.

Abstract: The invention relates to a method for operating an electrical machine (1) controlled by an inverter (2), wherein the inverter (2) comprises half-bridge branches (10-U, 10-V, 10-W) having power components in the form of controllable power switching elements (3) and power diodes (4) respectively connected in parallel therewith, wherein each of the half-bridge branches (10-U; 10-V; 10-W) is arranged on a separate semiconductor module (11-U; 11-V; 11-W), which are arranged jointly on a baseplate (12), wherein the phase currents (1_U, 1_V, 1_W) flowing through the half-bridge branches (10-U, 10-V, 10-W), the voltages present at the power components and temperatures (t_Sens_U, t Sens_V, t_Sens_W) on the semiconductor modules (11-U, 11-V, 11-W) are determined, from the current (1_U; 1_V; 1_W) respectively flowing at a power component and from the voltage respectively present a power loss (P) is calculated for each of the power components, from the power losses (P) a relevant temperature swing (?t; ?t_Sens) is determ

Abstract: A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates.

Abstract: Macroblock placement for an integrated circuit register-transfer level design is enhanced by tagging blocks having a set of functions as usage element definitions that have a minimum input signal width, such as tags added to a netlist of the design. Tagged blocks aid preferred and regular placement of library cells that are morphed to adapt for reduced congestion and improved utilization.

Abstract: An improved method for performing a write through operation during a write operation of a SRAM cell (10) of a SRAM array (1) is disclosed. The method comprises suppressing a false write through data propagation at an output node (C, F) of the SRAM array (1) in case of a failure causing transition at a first node (t) or a second node (c) of the SRAM cell (10) by using information about the input data (data, data_b) to be written in the SRAM cell (10) and read data propagation paths to retain the output node (C, F) after a global bit line (gb_t, gb_c) at a precharge level independently from a logical level of the global bit line (gb_t, gb_c), if a corresponding node (c, t) of the SRAM cell (10) is performing the failure causing transition based on input data (data, data_b) to be written in the SRAM cell (10).

Abstract: A memory array includes a plurality of memory cells, wherein each cell of the plurality of memory cells is defined by a row and a column, wherein each row includes a unique identifying address, and wherein each column is associated with one of two sets, the columns arranged such that a column associated with a first set is adjacent to a column of a second set.

Abstract: A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals.

Abstract: A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals.

Abstract: A method for configuring a n-way XOR/XNOR circuit comprises providing a plurality of top stacks of PFETs each including at least three PFETs electrically connected between a high logic level and an output logic connection, providing a plurality of bottom stacks of NFETs each including at least three NFETs electrically connected between a low logic level and the output logic connection, connecting a source or a drain of the outermost PFET in each top stack to a source or a drain of a corresponding NFET in each bottom stack to generate inverted logic signals, inputting at least three input logic states to the stacks of PFETs to selectively connect or disconnect the output logic connection to the high logic level, inputting at least three input logic states to the stacks of NFETs to selectively connect or disconnect the output logic connection to the low logic level, and outputting a logic signal from the output logic connection.

Abstract: A method implemented as a computer program product for comparing two designs of electronic circuits, wherein the design representations comprise several hierarchically related sheets. The method comprises the steps of (a) identifying corresponding top-sheets of the first hierarchy level in the design versions; (b) generating a list of all sub-sheets for each top-sheet and comparing the lists to identify added, removed and common sheets of the corresponding top-sheets; (c) defining the common sheets as corresponding top-sheets of a next hierarchy level; and (d) repeating steps (a)-(c) until at least one of the top-sheets does not comprise any sub-sheet.

Abstract: According to the present invention an automated layout generator is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.

Abstract: A Tri-State circuit element (100) composed of Complementary Metal Oxide Semiconductor (CMOS)—devices is described. Said Tri-State circuit element (100) having a data signal input terminal (102) for receiving a data signal, an enable signal input terminal (104) for receiving an enable signal, and an output signal terminal (106) for providing an output signal. Furthermore a Tri-State-Multiplexer circuitry (300) composed of such Tri-State circuit elements (100) is described.

Abstract: A method for comparing two designs of electronic circuits, especially for comparing different versions of a design for an electronic circuit, wherein the design representations comprise several hierarchically related sheets. The method comprises the steps of: a) analyzing the hierarchies of said design versions to identify added, removed and common sheets; b) determining differences between common sheets to identify modified sheets; and c) visualizing the combined hierarchies of said design versions wherein added, removed and modified sheets are marked.