Patents by Inventor Todd Merritt
Todd Merritt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11914530Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: GrantFiled: July 14, 2022Date of Patent: February 27, 2024Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Patent number: 11763906Abstract: Methods, systems, and devices for degradation signaling for a memory device are described. In one example, a method in accordance with the described techniques may include monitoring, at a memory device, an operational characteristic of the memory device. For example, the threshold voltage of one or more transistors within the memory device may be monitored. The memory device may identify a degradation of the memory device based at least in part on the monitored operational characteristic. Based on identifying the degradation, the memory device may signal, to a host device, an indication of the degradation of the memory device.Type: GrantFiled: December 20, 2018Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventor: Todd A. Merritt
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Publication number: 20220350760Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: ApplicationFiled: July 14, 2022Publication date: November 3, 2022Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Patent number: 11403240Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: GrantFiled: October 7, 2016Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Publication number: 20200202965Abstract: Methods, systems, and devices for degradation signaling for a memory device are described. In one example, a method in accordance with the described techniques may include monitoring, at a memory device, an operational characteristic of the memory device. For example, the threshold voltage of one or more transistors within the memory device may be monitored. The memory device may identify a degradation of the memory device based at least in part on the monitored operational characteristic. Based on identifying the degradation, the memory device may signal, to a host device, an indication of the degradation of the memory device.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventor: Todd A. Merritt
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Publication number: 20170024337Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: ApplicationFiled: October 7, 2016Publication date: January 26, 2017Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Patent number: 9477636Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: GrantFiled: October 21, 2009Date of Patent: October 25, 2016Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Patent number: 9082466Abstract: Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.Type: GrantFiled: July 23, 2013Date of Patent: July 14, 2015Assignee: Micron Technology, Inc.Inventors: Zhong-Yi Xia, Vikram K. Bollu, Jonathan L. Gossi, Howard C. Kirsch, Todd A. Merritt
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Publication number: 20150029804Abstract: Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.Type: ApplicationFiled: July 23, 2013Publication date: January 29, 2015Applicant: Micron Technology, Inc.Inventors: Zhong-Yi Xia, Vikram K. Bollu, Jonathan L. Gossi, Howard C. Kirsch, Todd A. Merritt
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Patent number: 8743628Abstract: Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.Type: GrantFiled: August 8, 2011Date of Patent: June 3, 2014Assignee: Micron Technology, Inc.Inventors: Tae H. Kim, Howard C. Kirsch, Yu-Wen Huang, Mingshiang Wang, Todd A. Merritt
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Patent number: 8644103Abstract: Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.Type: GrantFiled: February 1, 2011Date of Patent: February 4, 2014Assignee: Micron Technology, Inc.Inventors: Yantao Ma, Todd Merritt
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Publication number: 20130039132Abstract: Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Inventors: Tae H. Kim, Howard C. Kirsch, Yu-Wen Huang, Mingshiang Wang, Todd A. Merritt
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Patent number: 8213244Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.Type: GrantFiled: October 18, 2011Date of Patent: July 3, 2012Assignee: Round Rock Research, LLCInventors: Todd A. Merritt, Troy A. Manning
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Patent number: 8143966Abstract: Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of differential pairs of lines. Each differential pair has two lines including one or more parallel portions extending substantially parallel to each other. Each pair also includes a shield line. Each of the shield lines includes one or more parallel portions interposed between the parallel portions of one of the pairs of differential lines. One or more of the shield lines are electrically connected to a voltage reference, such as ground. This layout is believed to reduce or eliminate intra-pair coupling as well as inter-pair coupling.Type: GrantFiled: October 12, 2010Date of Patent: March 27, 2012Assignee: Micron Technology, Inc.Inventor: Todd Merritt
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Publication number: 20120033513Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.Type: ApplicationFiled: October 18, 2011Publication date: February 9, 2012Applicant: ROUND ROCK RESEARCH, LLCInventors: Todd A. Merritt, Troy A. Manning
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Patent number: 8107304Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory.Type: GrantFiled: December 18, 2009Date of Patent: January 31, 2012Assignee: Round Rock Research, LLCInventors: Todd A. Merritt, Troy A. Manning
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Publication number: 20110122720Abstract: Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.Type: ApplicationFiled: February 1, 2011Publication date: May 26, 2011Applicant: Micron Technology, Inc.Inventors: Yantao Ma, Todd Merritt
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Publication number: 20110093662Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: ApplicationFiled: October 21, 2009Publication date: April 21, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Patent number: 7894285Abstract: Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.Type: GrantFiled: November 13, 2008Date of Patent: February 22, 2011Assignee: Micron Technology, Inc.Inventors: Yantao Ma, Todd Merritt
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Publication number: 20110025428Abstract: Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of differential pairs of lines. Each differential pair has two lines including one or more parallel portions extending substantially parallel to each other. Each pair also includes a shield line. Each of the shield lines includes one or more parallel portions interposed between the parallel portions of one of the pairs of differential lines. One or more of the shield lines are electrically connected to a voltage reference, such as ground. This layout is believed to reduce or eliminate intra-pair coupling as well as inter-pair coupling.Type: ApplicationFiled: October 12, 2010Publication date: February 3, 2011Applicant: Micron Technology, Inc.Inventor: Todd Merritt