Abstract: An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near a nay sense amplifiers are used to control write is data drivers to provide for maximum write times without crossing current during input/output line equilibration periods.

Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

Abstract: A memory integrated circuit can be used either alone or as a pair to provide a memory device having twice the capacity of the single integrated circuit. The larger capacity memory device is addressed using an extra row address bit. The extra row address bit is used either to alternately enable each of the memory integrated circuits in one configuration or is remapped to become an extra column address bit in another configuration.

Abstract: A memory integrated circuit can be used either alone or as a pair to provide a memory device having twice the capacity of the single integrated circuit. The larger capacity memory device is addressed using an extra row address bit. The extra row address bit is used either to alternately enable each of the memory integrated circuits in one configuration or is remapped to become an extra column address bit in another configuration.

Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory.

Abstract: A high output, high efficiency charge pump is disclosed and claimed. The charge pump includes a charge storage device. A pre-charge circuit is connected to the charge storage device to charge the charge storage device to a charge level to provide a predetermined output voltage from the charge pump. A blocking circuit is provided to prevent charge leakage from the charge storage device to the pre-charge circuit.

Abstract: The charge pump circuit includes an oscillator to generate an oscillating signal. The charge pump circuit further includes a primary phase generator, which receives the oscillating signal and generates first and a second phase signals that are non-overlapping and crossing around their high points. The primary phase generates further generates third and fourth phase signals that non-overlapping and crossing around their low points. The charge pump circuit further includes a secondary phase generator, which receives the first and second phase signals from the primary phase generator and generates delayed fifth and sixth phase signals. The charge circuit further includes first and second pre-boot precharge capacitors, which receive the first and second phase signals.

Abstract: A data amplifier configured to allow for fewer data lines and/or increased processing speeds. Specifically, multiple helper flip-flops are used to prefetch data in a data amplifier. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines. Alternatively, the number of data lines can be maintained and faster bus processing speeds may be realized.

Abstract: A memory integrated circuit can be used either alone or as a pair to provide a memory device having twice the capacity of the single integrated circuit. The larger capacity memory device is addressed using an extra row address bit. The extra row address bit is used either to alternately enable each of the memory integrated circuits in one configuration or is remapped to become an extra column address bit in another configuration.

Abstract: A memory device includes a control circuit for initiating a read operation and a write operation in response to a combination of input signals during a setup time. The setup time is a time interval during which all input signals must remain valid before a next appearance of a rising edge of a clock signal. The control circuit uses the setup time to send a signal from one part of the memory to another part of the memory to avoid a signal propagation delay time. The memory device also includes a circuit for preparing the memory device for the write operation before the setup time.

Abstract: An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal. A method for testing a memory device having a plurality of data lines includes reading data present on at least a subset of the plurality of data lines.

Abstract: A voltage pump and method of driving a node to an increased potential. A periodic input signal is fed into a precharged small capacitor to create a level shifted periodic intermediate potential at an intermediate node. The intermediate node is a supply node to a level translator circuit. The output of the level translator circuit controls the actuation of a pass transistor. When actuated the pass transistor drives a boosted potential to an output node of the voltage pump circuit. In one embodiment the level translator circuit has a delay element which maintains the deactivation of a pull down portion of the level translator circuit until a pull up portion of the level translator circuit is deactivated. A first diode clamp is used to limit the output of the level translator circuit and the boosted potential to within 1 threshold voltage (of the diode clamp) of each other.

Abstract: An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal.

Abstract: A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

Abstract: An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods.

Abstract: A method and apparatus for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines.

Abstract: A memory having a control circuit for initiating a read or a write operation in response to a combination of input signals during a setup time is described. The setup time is a specified time period during which all inputs must remain valid before a next appearance of a rising edge of a clock signal. The control circuit uses the setup time to send a signal from one part of the memory to another part of the memory to avoid the propagation delay time. Further, a circuit is provided which prepares the memory for a write operation prior to the setup time.

Abstract: The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more “planes.” Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory.

Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.