Patents by Inventor Tofizur RAHMAN

Tofizur RAHMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11063088
    Abstract: A memory device includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) between the first electrode and the second electrode. The MTJ includes a fixed magnet, a free magnet and a tunnel barrier between the fixed magnet and the free magnet. The MTJ further includes a conductive layer between the free magnet and the second electrode, the conductive layer having a metallic dopant, where the metallic dopant has a concentration that increase with distance from an interface between the free magnet and the conductive layer. A capping layer is between the conductive layer and the second electrode.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Daniel Ouellette, Christopher Wiegand, Justin Brockman, Tofizur Rahman, Oleg Golonzka, Angeline Smith, Andrew Smith, James Pellegren, Aaron Littlejohn, Juan G. Alzate-Vinasco, Yu-Jin Chen, Tanmoy Pramanik
  • Patent number: 11062752
    Abstract: A perpendicular spin orbit torque memory device includes a first electrode having tungsten and at least one of nitrogen or oxygen and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first magnet, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Tofizur Rahman, James Pellegren, Angeline Smith, Christopher Wiegand, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Benjamin Buford, Ian Young
  • Publication number: 20210175284
    Abstract: A memory device includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) between the first electrode and the second electrode. The MTJ includes a fixed magnet, a free magnet and a tunnel barrier between the fixed magnet and the free magnet. The MTJ further includes a conductive layer between the free magnet and the second electrode, the conductive layer having a metallic dopant, where the metallic dopant has a concentration that increase with distance from an interface between the free magnet and the conductive layer. A capping layer is between the conductive layer and the second electrode.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Applicant: Intel Corporation
    Inventors: Daniel Ouellette, Christopher Wiegand, Justin Brockman, Tofizur Rahman, Oleg Golonzka, Angeline Smith, Andrew Smith, James Pellegren, Aaron Littlejohn, Juan G. Alzate-Vinasco, Yu-Jin Chen, Tanmoy Pramanik
  • Patent number: 11031545
    Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz
  • Patent number: 10943950
    Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Daniel Ouellette, Christopher Wiegand, Justin Brockman, Tofizur Rahman, Oleg Golonzka, Angeline Smith, Andrew Smith, James Pellegren, Aaron Littlejohn, Michael Robinson, Huiying Liu
  • Patent number: 10868233
    Abstract: Strain engineering of perpendicular magnetic tunnel junctions (PMTJs) is described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz, Oleg Golonzka, Justin S. Brockman, Kevin P. O'Brien, Brian S. Doyle, Kaan Oguz, Tahir Ghani, Mark L. Doczy
  • Patent number: 10847714
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, Md Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Publication number: 20200343301
    Abstract: A memory apparatus includes a first electrode having a spin orbit material. The memory apparatus further includes a first memory device on a portion of the first electrode and a first dielectric adjacent to a sidewall of the first memory device. The memory apparatus further includes a second memory device on a portion of the first electrode and a second dielectric adjacent to a sidewall of the second memory device. A second electrode is on and in contact with a portion of the first electrode, where the second electrode is between the first memory device and the second memory device. The second electrode has a lower electrical resistance than an electrical resistance of the first electrode. The memory apparatus further includes a first interconnect structure and a second interconnect, each coupled with the first electrode.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Inventors: Benjamin Buford, Angeline Smith, Noriyuki Sato, Tanay Gosavi, Kaan Oguz, Christopher Wiegand, Kevin O'Brien, Tofizur Rahman, Gary Allen, Sasikanth Manipatruni, Emily Walker
  • Patent number: 10804460
    Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Daniel G. Ouellette, Kevin P. O'Brien, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, Daniel B. Bergstrom, Justin S. Brockman, Oleg Golonzka, Tahir Ghani
  • Publication number: 20200313075
    Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Noriyuki SATO, Angeline SMITH, Tanay GOSAVI, Sasikanth MANIPATRUNI, Kaan OGUZ, Kevin O'Brien, Benjamin BUFORD, Tofizur RAHMAN, Rohan PATIL, Nafees KABIR, Michael CHRISTENSON, Ian YOUNG, Hui Jae YOO, Christopher WIEGAND
  • Publication number: 20200312907
    Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Daniel Ouellette, Christopher Wiegand, Justin Brockman, Tofizur Rahman, Oleg Golonzka, Angeline Smith, Andrew Smith, James Pellegren, Aaron Littlejohn, Michael Robinson, Huiying Liu
  • Publication number: 20200313084
    Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode and a magnetic junction directly on the conductive layer. The magnetic junction further includes a pinning structure above the conductive layer, a fixed magnet above the pinning structure, a tunnel barrier on the fixed magnet, a free magnet on the tunnel barrier layer and a second electrode above the free magnet. The conductive layer including iridium and the pinning structure including iridium provide switching efficiency.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Daniel Ouellette, Christopher Wiegand, Justin Brockman, Tofizur Rahman, Oleg Golonzka, Angeline Smith, Andrew Smith, James Pellegren, Michael Robinson, Huiying Liu
  • Publication number: 20200313074
    Abstract: A memory device includes a first electrode, a second electrode and a magnetic junction between the first and the second electrode. The magnetic junction includes a first magnetic structure that includes a first magnet including an alloy of cobalt and tungsten, and a second magnet above the first magnet. The first and the second magnets are separated by a non-magnetic spacer layer. The magnetic junction further includes a layer including a metal and oxygen on the first magnetic structure. The tunnel barrier layer has an <001> crystal texture. The magnetic junction further includes a third magnet on the tunnel barrier layer. The third magnet has a magnetization which can change in response to torque from a current tunneling through the tunnel barrier layer.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Angeline Smith, Daniel Ouellette, Christopher Wiegand, Justin Brockman, Tofizur Rahman, Oleg Golonzka, Andrew Smith, James Pellegren
  • Patent number: 10770651
    Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bilayers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: MD Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 10732217
    Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Kaan Oguz, Christopher J. Wiegand, Mark L. Doczy, Brian S. Doyle, MD Tofizur Rahman, Oleg Golonzka, Tahir Ghani
  • Publication number: 20200227474
    Abstract: A perpendicular spin orbit memory device includes a first electrode having a magnetic material and platinum and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first electrode, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.
    Type: Application
    Filed: January 11, 2019
    Publication date: July 16, 2020
    Inventors: Kevin O'Brien, Christopher Wiegand, Tofizur Rahman, Noriyuki Sato, Gary Allen, James Pellegren, Angeline Smith, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Benjamin Buford, Ian Young
  • Publication number: 20200227104
    Abstract: A perpendicular spin orbit torque memory device includes a first electrode having tungsten and at least one of nitrogen or oxygen and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first magnet, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.
    Type: Application
    Filed: January 11, 2019
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Tofizur Rahman, James Pellegren, Angeline Smith, Christopher Wiegand, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Benjamin Buford, Ian Young
  • Patent number: 10636960
    Abstract: MTJ material stacks with a laterally strained free magnetic layer, STTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular pMTJ material stacks included free magnetic layers that are compressively strained laterally by a surrounding material, which increases coercive field strength for a more stable device. In some embodiments, a pMTJ material stack is encased in a compressive-stressed material. In some further embodiments, a pMTJ material stack is encased first in a dielectric shell, permitting a conductive material to be deposited over the shell as the compressive-stressed, strain-inducing material layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Prashanth P. Madras, MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Oleg Golonzka, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Tahir Ghani, Kaan Oguz
  • Publication number: 20200105998
    Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet, a fixed magnet and a tunnel barrier layer in between, where at least one of the fixed magnet or the free magnet includes two magnetic layers and a spacer layer comprising tungsten in between.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Angeline SMITH, Sasikanth MANIPATRUNI, Christopher WIEGAND, Tofizur RAHMAN, Noriyuki SATO, Benjamin BUFORD
  • Publication number: 20200105324
    Abstract: A magnetic tunnel junction (MTJ) for use in a magnetic spin orbit torque random access memory device (SOT MRAM) is described. Magnetic tunnel junctions described herein include a multi-magnet free layer over a spin orbit torque electrode. The multi-magnet free layer includes at least three sub-layers: a first magnetic sub-layer in direct contact with the SOT electrode having a first magnetic stability, a second magnetic sub-layer having a second magnetic stability greater than the first magnetic stability, and a magnetic coupling layer between the first and second sub-layers.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Angeline Smith, Sasikanth Manipatruni, MD Tofizur Rahman, Noriyuki Sato, Tanay Gasovi, Christopher Wiegand, Ian Young