Patents by Inventor Tohru Okabe
Tohru Okabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12167624Abstract: A display device includes: a base substrate; a thin-film transistor layer provided on the base substrate, a light-emitting element layer provided on the thin-film transistor layer; and a sealing film provided on the light-emitting element. Each of light-emitting elements includes: a first electrode; a functional layer; and a second electrode stacked on top of another in a stated order. The display device includes: a display region; a frame region; and a non-display region. The non-display region includes a through hole. The display device includes a separation wall shaped into a frame and provided to the non-display region along an edge of the through hole. The separation wall includes: a first resin layer: and a first metal layer provided on the first resin layer. The first metal layer includes a first protrusion shaped into a canopy, and protruding from the first resin layer toward the display region.Type: GrantFiled: February 27, 2019Date of Patent: December 10, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Shinsuke Saida, Ryosuke Gunji, Shinji Ichikawa, Hiroharu Jinmura, Akira Inoue, Yoshihiro Nakada
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Patent number: 12167633Abstract: A separation wall is provided in a frame-like shape along a peripheral edge of a through-hole in a non-display region which is defined to be in an island shape inside a display region and in which the through-hole is formed, the separation wall includes an inner metal layer provided in a frame-like shape on a first inorganic insulating film on a side of the through-hole, and a resin layer provided in a frame-like shape on the first inorganic insulating film and the inner metal layer, and the resin layer includes an inner protrusion portion provided in an eaves shape and protruding from the inner metal layer.Type: GrantFiled: March 1, 2019Date of Patent: December 10, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Ryosuke Gunji, Shinsuke Saida, Shinji Ichikawa, Hiroharu Jinmura, Yoshihiro Nakada, Akira Inoue, Takeshi Yaneda
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Patent number: 12161031Abstract: A display device includes a thin film transistor layer including a first interlayer insulation film, a first wiring layer, a second interlayer insulation film, a second wiring layer, a third interlayer insulation film, a third wiring layer, a first planarization film, a fourth wiring layer, and a second planarization film; and a first damming wall in a frame area separated from the first and second planarization film in a display area by a first slit. There is provided a fourth interlayer insulation film between the third and fourth wiring layer. The fourth interlayer insulation film covers an edge of either one or both of a first frame line and a second frame line as the third wiring layer in a region where the first frame line is located opposite the second frame line in a plan view, the edge facing the display area and being exposed in the first slit.Type: GrantFiled: October 21, 2019Date of Patent: December 3, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Takeshi Yaneda
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Publication number: 20240397769Abstract: A terminal portion provided in a frame region around a display region is provided with a resin substrate, an inorganic layered film provided above the resin substrate, a pad column provided above the inorganic layered film, the pad column including a plurality of pads arranged in a row electrically connected to a plurality of bumps provided on an IC chip via an ACF, and a flattening film including an organic insulating film provided above the inorganic layered film and the pad column, the flattening film covering an end portion of each of the plurality of pad, and an opening exposing the inorganic layered film is formed in the flattening film.Type: ApplicationFiled: November 2, 2021Publication date: November 28, 2024Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
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Publication number: 20240381743Abstract: An organic EL display device has a picture-frame region provided with: dam walls extending along an outer periphery of a display region to block an organic sealing layer; and a second lead wire running from toward the display region, crossing the dam walls, and extending out of the picture-frame region. The picture-frame region includes a spacer wall extending along the dam wall and provided to an outer periphery of a portion, of the dam wall, intersecting at least with the second lead wire. The spacer wall has an upper portion provided with a plurality of protruding portions at intervals along the spacer wall. The second lead wire extends to cross a portion of, the spacer wall, away from the protruding portions.Type: ApplicationFiled: May 19, 2021Publication date: November 14, 2024Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
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Patent number: 12120927Abstract: A TFT layer and an organic EL element layer are provided in this order on a resin substrate layer, the TFT layer includes source wiring lines, high-level power source wiring lines, conductive portions including connection wiring lines between TFTs, and a flattening film covering the conductive portions provided on the interlayer insulating film, a frame region is provided with a bending portion including a portion where a slit is formed in an inorganic insulating film including the interlayer insulating film, and a flattening auxiliary film is provided between each adjacent ones of the conductive portions, formed of a material identical to a material of the frame flattening film that fills the slit of the bending portion, in a layer identical to a layer of the frame flattering film, and covered with the flattening film together with the conductive portions.Type: GrantFiled: September 28, 2018Date of Patent: October 15, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Ryosuke Gunji, Tohru Okabe, Shinsuke Saida, Hiroki Taniyama, Shinji Ichikawa, Akira Inoue, Yoshihiro Nakada, Hiroharu Jinmura, Koji Tanimura, Yoshihiro Kohara
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Patent number: 12101974Abstract: A TFT layer of a display device includes: an initialization power source wiring line; a second interlayer insulating film provided covering the initialization power source wiring line; a source wiring line provided on the second interlayer insulating film; a low-level power source wiring line provided below the initialization power source wiring line; and a frame capacitor. The frame capacitor includes: a first frame capacitance electrode formed by the same material in the same layer as the initialization power source wiring line; and a second frame capacitance electrode formed by the same material in the same layer as the source wiring line and facing the first frame capacitance electrode with the second interlayer insulating film interposed therebetween. The first frame capacitance electrode is electrically connected to the high-level power source wiring line, and the second frame capacitance electrode is electrically connected to the low-level power source wiring line.Type: GrantFiled: March 28, 2019Date of Patent: September 24, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Takeshi Yaneda
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Patent number: 12089444Abstract: In a TFT layer forming step, first, a semiconductor layer on a resin substrate is formed by performing a semiconductor layer forming step, and subsequently a gate insulating film is formed to cover the semiconductor layer by performing a gate insulating film forming step, and then a first metal layer is formed by performing a first metal film deposition step, a first photo step, and a first etching step, and a second metal layer is formed by performing a second metal film deposition step, a second photo step, and a second etching step, thereby forming a gate layer in which the first metal layer and the second metal layer are layered.Type: GrantFiled: February 27, 2019Date of Patent: September 10, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Takeshi Yaneda
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Patent number: 12089463Abstract: A display device according to an aspect of the disclosure includes a first metal protrusion being in contact with a first power-source trunk wire, and a second metal protrusion being in contact with a second power-source trunk wire. A first bank defining the end of an organic sealing film includes the first metal protrusion, the second metal protrusion, and a first resin protrusion. The first resin protrusion overlaps the first and second metal protrusions. The first resin protrusion has a frame shape.Type: GrantFiled: September 19, 2019Date of Patent: September 10, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Ryosuke Gunji, Akira Inoue, Yoshihiro Nakada, Hiroharu Jinmura
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Patent number: 12082449Abstract: A separation wall is provided in a frame shape along a circumferential edge of a through-hole in a non-display region, in which the through-hole is formed, defined in an island shape inside a display region. The separation wall includes a wall base portion provided in a frame shape by a part of a second interlayer insulating film and a resin layer provided in an eave shape on the wall base portion to extend to a through-hole side and a display region side. Opening portions opening upward are provided on peripheries of the wall base portion on the through-hole side and the display region side in the second interlayer insulating film.Type: GrantFiled: March 29, 2019Date of Patent: September 3, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Shinsuke Saida, Shinji Ichikawa, Ryosuke Gunji, Tohru Okabe, Akira Inoue, Yoshihiro Nakada, Hiroharu Jinmura
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Patent number: 11997889Abstract: Frame wiring lines are provided in a frame region, a flattening film in which a frame-shaped slit is formed in the frame region is provided in the display region and the frame region, a plurality of first electrodes constituting light-emitting elements are provided on the flattening film, and conductive layer made of the same material and formed in the same layer as those of each of the plurality of first electrodes are provided covering at least end faces of the frame wiring lines exposed from the slit.Type: GrantFiled: March 30, 2018Date of Patent: May 28, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Hiroki Taniyama, Ryosuke Gunji, Shinsuke Saida, Shinji Ichikawa, Tohru Okabe, Kohji Ariga, Akira Inoue, Yoshihiro Kohara, Koji Tanimura, Yoshihiro Nakada, Hiroharu Jinmura
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Publication number: 20240164151Abstract: Provided is the following: a resin substrate layer; a thin-film transistor layer provided on the resin substrate layer, and having a stack of, in sequence, a gate insulating film, an interlayer insulating film, and a flattening film; and a light-emitting element layer provided on the thin-film transistor layer, with a plurality of first electrodes, a common edge cover that is common, a plurality of light-emitting function layers, and a second electrode that is common being stacked sequentially in correspondence with a plurality of subpixels constituting a display region. A non-display region that is in the form of an island within the display region has a through-hole. The non-display region includes a first light-blocking film provided on the periphery of the flattening film so as to cover the side wall of the periphery.Type: ApplicationFiled: March 31, 2021Publication date: May 16, 2024Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
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Publication number: 20240147789Abstract: A display device, includes: a base substrate layer; a thin-film transistor layer provided on the base substrate layer, and including a plurality of subpixels forming a display region, each of the subpixels being provided with a thin-film transistor on which a planarization film is stacked; and a light-emitting element layer provided on the thin-film transistor layer, and including a plurality of first electrodes, a common edge cover, a plurality of light-emitting functional layers, and a common second electrode, all of which are sequentially stacked on top of another in association with the plurality of subpixels, wherein each of the first electrodes has a peripheral edge portion provided to: surround, in plan view, the thin-film transistor corresponding to the first electrode; and protrude toward the base substrate layer.Type: ApplicationFiled: April 27, 2021Publication date: May 2, 2024Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
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Patent number: 11968861Abstract: An organic EL display (1) has a bend (B) where a slit (81) is bored in a base coat film (23), gate insulating film (27), first interlayer insulating film (31) and second interlayer insulating film (35). The bend is provided with a filler layer (83) filling the slit and covering both edges of the slit. The filler layer has a protrusion (85) overlapping each edge in the width direction of the slit. A routed wire (7) routed from the display region (D) and then routed over the filler layer to reach a terminal section (T) extends over the protrusion.Type: GrantFiled: April 4, 2019Date of Patent: April 23, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Shinji Ichikawa, Shinsuke Saida, Ryosuke Gunji, Hiroki Taniyama, Tohru Okabe, Akira Inoue, Hiroharu Jinmura, Yoshihiro Nakada, Koji Tanimura
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Patent number: 11957014Abstract: A display device includes: a plurality of control lines; a plurality of power supply lines; a plurality of data signal lines; an oxide semiconductor layer; a first metal layer; a gate insulation film; a first inorganic insulation film; a second metal layer; a second inorganic insulation film; and a third metal layer. The oxide semiconductor layer, in a plan view, contains therein semiconductor lines formed as isolated regions between a plurality of drivers and a display area. The semiconductor lines cross the plurality of control lines and the plurality of power supply lines, are in contact with the plurality of control lines via an opening in a gate insulation film, are in contact with the plurality of power supply lines via an opening in the first inorganic insulation film, and have a plurality of narrowed portions, such that thicker and thinner regions exist along the same line.Type: GrantFiled: July 30, 2018Date of Patent: April 9, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Hiroharu Jinmura, Akira Inoue
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Patent number: 11957015Abstract: A lead wiring line is provided in a frame region to extend therein while intersecting with a frame-shaped dam wall, is formed of a same material and in a same layer as each of a plurality of display wiring lines in which a first metal layer, a second metal layer, and a third metal layer are layered in sequence, is electrically connected to the plurality of display wiring lines on a display region side, and is electrically connected to a terminal on a terminal portion side. The third metal layer is provided to cover a side surface of the first metal layer, and a side surface and an upper face of the second metal layer.Type: GrantFiled: September 25, 2018Date of Patent: April 9, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Takeshi Yaneda
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Patent number: 11950462Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.Type: GrantFiled: March 30, 2018Date of Patent: April 2, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Akira Inoue, Hiroharu Jinmura, Takeshi Yaneda
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Patent number: 11925078Abstract: A display device includes the following: a resin substrate; a TFT layer disposed on the resin substrate, the TFT layer having a stack of, in sequence, a base coat film, a semiconductor film, a gate insulating film, a first metal film, an interlayer insulating film, a second metal film, and a flattening film; a light-emitting element disposed on the TFT layer and forming a display region; and a plurality of TFTs disposed in the TFT layer in the display region. The base coat film includes an amorphous silicon film disposed at least all over the display region.Type: GrantFiled: September 21, 2018Date of Patent: March 5, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tokuo Yoshida, Tohru Okabe
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Patent number: 11908873Abstract: An active matrix substrate including a resin substrate including a plurality of external connection terminals arranged near a display region, the active matrix substrate includes: a plurality of first lead wires each extending from one of the external connection terminals to the display region; and a plurality of second lead wires each extending from one of the external connection terminals to a separation line, the second lead wires being arranged with an arrangement pitch along the separation line, and the arrangement pitch of the second lead wires being greater than an arrangement pitch of the first lead wires.Type: GrantFiled: August 23, 2018Date of Patent: February 20, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Ryosuke Gunji, Shinji Ichikawa, Shinsuke Saida, Shoji Okazaki, Tokuo Yoshida, Hiroki Taniyama, Kohji Ariga, Hiroharu Jinmura, Akira Inoue, Yoshihiro Nakada, Yoshihiro Kohara, Koji Tanimura
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Patent number: 11889729Abstract: A display device includes a short ring TFT, wherein the short ring TFT includes a semiconductor layer, a first gate electrode, a second gate electrode, a first gate insulating film provided between the semiconductor layer and the first gate electrode, and a second gate insulating film provided between the semiconductor layer and the second gate electrode, one of a pair of adjacent lead-out wiring lines is electrically connected to a source region of the semiconductor layer, the other of the pair of adjacent lead-out wiring lines is electrically connected to a drain region of the semiconductor layer, one of the first gate electrode and the second gate electrode is electrically connected to the source region or the drain region, and the other of the first gate electrode and the second gate electrode is electrically connected to a threshold value control wiring line.Type: GrantFiled: August 31, 2018Date of Patent: January 30, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Takeshi Yaneda