Patents by Inventor Tohru Okabe

Tohru Okabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063889
    Abstract: A separation wall is provided in a frame-like shape along a peripheral edge of a through-hole in a non-display region which is defined to be in an island shape inside a display region and in which the through-hole is formed, the separation wall includes an inner metal layer provided in a frame-like shape on a first inorganic insulating film on a side of the through-hole, and a resin layer provided in a frame-like shape on the first inorganic insulating film and the inner metal layer, and the resin layer includes an inner protrusion portion provided in an eaves shape and protruding from the inner metal layer.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Inventors: TOHRU OKABE, RYOSUKE GUNJI, SHINSUKE SAIDA, SHINJI ICHIKAWA, HIROHARU JINMURA, YOSHIHIRO NAKADA, AKIRA INOUE, TAKESHI YANEDA
  • Publication number: 20250063920
    Abstract: A display device includes: a thin film transistor layer including a first inorganic insulating film, a first metal layer, a second inorganic insulating film, a second metal layer, and a flattening resin film layered in order; and a light-emitting element layer. A slit is provided in the first and second inorganic insulating film in a bending portion. A filled resin film fills the slit. On the filled resin film, a plurality of lead wiring lines are provided in the same layer as the second metal layer. At least one lead wiring lines is electrically connected to a first and second lower wiring line provided in the same layer as the first metal layer and extending to a display region side and a terminal portion side via a first and second contact hole formed in a layered film including the second inorganic insulating film and the filled resin film.
    Type: Application
    Filed: February 24, 2022
    Publication date: February 20, 2025
    Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
  • Patent number: 12232365
    Abstract: A display device (2) includes: a planarization film; and a light-emitting-element layer including an anode, an edge cover, an EL active layer, and a cathode in this sequence. The display device further includes: a first photospacer and a second photospacer each having a surface thereof covered by the cathode; and a lightning rod photospacer (44) including a second projection portion (44b) that is a part of the planarization film and having a surface thereof covered by a first metal film (44c) made of the same material and in the same layer as the anode.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: February 18, 2025
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shoji Okazaki, Tohru Okabe
  • Publication number: 20250056965
    Abstract: A display device includes: a base substrate; a thin-film transistor layer provided on the base substrate, a light-emitting element layer provided on the thin-film transistor layer, and a sealing film provided on the light-emitting element. Each of light-emitting elements includes: a first electrode; a functional layer, and a second electrode stacked on top of another in a stated order. The display device includes: a display region; a frame region; and a non-display region. The non-display region includes a through hole. The display device includes a separation wall shaped into a frame and provided to the non-display region along an edge of the through hole. The separation wall includes: a first resin layer, and a first metal layer provided on the first resin layer. The first metal layer includes a first protrusion shaped into a canopy, and protruding from the first resin layer toward the display region.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Inventors: TOHRU OKABE, SHINSUKE SAIDA, RYOSUKE GUNJI, SHINJI ICHIKAWA, HIROHARU JINMURA, AKIRA INOUE, YOSHIHIRO NAKADA
  • Patent number: 12167633
    Abstract: A separation wall is provided in a frame-like shape along a peripheral edge of a through-hole in a non-display region which is defined to be in an island shape inside a display region and in which the through-hole is formed, the separation wall includes an inner metal layer provided in a frame-like shape on a first inorganic insulating film on a side of the through-hole, and a resin layer provided in a frame-like shape on the first inorganic insulating film and the inner metal layer, and the resin layer includes an inner protrusion portion provided in an eaves shape and protruding from the inner metal layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 10, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Shinsuke Saida, Shinji Ichikawa, Hiroharu Jinmura, Yoshihiro Nakada, Akira Inoue, Takeshi Yaneda
  • Patent number: 12167624
    Abstract: A display device includes: a base substrate; a thin-film transistor layer provided on the base substrate, a light-emitting element layer provided on the thin-film transistor layer; and a sealing film provided on the light-emitting element. Each of light-emitting elements includes: a first electrode; a functional layer; and a second electrode stacked on top of another in a stated order. The display device includes: a display region; a frame region; and a non-display region. The non-display region includes a through hole. The display device includes a separation wall shaped into a frame and provided to the non-display region along an edge of the through hole. The separation wall includes: a first resin layer: and a first metal layer provided on the first resin layer. The first metal layer includes a first protrusion shaped into a canopy, and protruding from the first resin layer toward the display region.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: December 10, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Ryosuke Gunji, Shinji Ichikawa, Hiroharu Jinmura, Akira Inoue, Yoshihiro Nakada
  • Patent number: 12161031
    Abstract: A display device includes a thin film transistor layer including a first interlayer insulation film, a first wiring layer, a second interlayer insulation film, a second wiring layer, a third interlayer insulation film, a third wiring layer, a first planarization film, a fourth wiring layer, and a second planarization film; and a first damming wall in a frame area separated from the first and second planarization film in a display area by a first slit. There is provided a fourth interlayer insulation film between the third and fourth wiring layer. The fourth interlayer insulation film covers an edge of either one or both of a first frame line and a second frame line as the third wiring layer in a region where the first frame line is located opposite the second frame line in a plan view, the edge facing the display area and being exposed in the first slit.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 3, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Takeshi Yaneda
  • Publication number: 20240397769
    Abstract: A terminal portion provided in a frame region around a display region is provided with a resin substrate, an inorganic layered film provided above the resin substrate, a pad column provided above the inorganic layered film, the pad column including a plurality of pads arranged in a row electrically connected to a plurality of bumps provided on an IC chip via an ACF, and a flattening film including an organic insulating film provided above the inorganic layered film and the pad column, the flattening film covering an end portion of each of the plurality of pad, and an opening exposing the inorganic layered film is formed in the flattening film.
    Type: Application
    Filed: November 2, 2021
    Publication date: November 28, 2024
    Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
  • Publication number: 20240381743
    Abstract: An organic EL display device has a picture-frame region provided with: dam walls extending along an outer periphery of a display region to block an organic sealing layer; and a second lead wire running from toward the display region, crossing the dam walls, and extending out of the picture-frame region. The picture-frame region includes a spacer wall extending along the dam wall and provided to an outer periphery of a portion, of the dam wall, intersecting at least with the second lead wire. The spacer wall has an upper portion provided with a plurality of protruding portions at intervals along the spacer wall. The second lead wire extends to cross a portion of, the spacer wall, away from the protruding portions.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 14, 2024
    Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
  • Patent number: 12120927
    Abstract: A TFT layer and an organic EL element layer are provided in this order on a resin substrate layer, the TFT layer includes source wiring lines, high-level power source wiring lines, conductive portions including connection wiring lines between TFTs, and a flattening film covering the conductive portions provided on the interlayer insulating film, a frame region is provided with a bending portion including a portion where a slit is formed in an inorganic insulating film including the interlayer insulating film, and a flattening auxiliary film is provided between each adjacent ones of the conductive portions, formed of a material identical to a material of the frame flattening film that fills the slit of the bending portion, in a layer identical to a layer of the frame flattering film, and covered with the flattening film together with the conductive portions.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 15, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Ryosuke Gunji, Tohru Okabe, Shinsuke Saida, Hiroki Taniyama, Shinji Ichikawa, Akira Inoue, Yoshihiro Nakada, Hiroharu Jinmura, Koji Tanimura, Yoshihiro Kohara
  • Patent number: 12101974
    Abstract: A TFT layer of a display device includes: an initialization power source wiring line; a second interlayer insulating film provided covering the initialization power source wiring line; a source wiring line provided on the second interlayer insulating film; a low-level power source wiring line provided below the initialization power source wiring line; and a frame capacitor. The frame capacitor includes: a first frame capacitance electrode formed by the same material in the same layer as the initialization power source wiring line; and a second frame capacitance electrode formed by the same material in the same layer as the source wiring line and facing the first frame capacitance electrode with the second interlayer insulating film interposed therebetween. The first frame capacitance electrode is electrically connected to the high-level power source wiring line, and the second frame capacitance electrode is electrically connected to the low-level power source wiring line.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 24, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Takeshi Yaneda
  • Patent number: 12089463
    Abstract: A display device according to an aspect of the disclosure includes a first metal protrusion being in contact with a first power-source trunk wire, and a second metal protrusion being in contact with a second power-source trunk wire. A first bank defining the end of an organic sealing film includes the first metal protrusion, the second metal protrusion, and a first resin protrusion. The first resin protrusion overlaps the first and second metal protrusions. The first resin protrusion has a frame shape.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 10, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Ryosuke Gunji, Akira Inoue, Yoshihiro Nakada, Hiroharu Jinmura
  • Patent number: 12089444
    Abstract: In a TFT layer forming step, first, a semiconductor layer on a resin substrate is formed by performing a semiconductor layer forming step, and subsequently a gate insulating film is formed to cover the semiconductor layer by performing a gate insulating film forming step, and then a first metal layer is formed by performing a first metal film deposition step, a first photo step, and a first etching step, and a second metal layer is formed by performing a second metal film deposition step, a second photo step, and a second etching step, thereby forming a gate layer in which the first metal layer and the second metal layer are layered.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 10, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Takeshi Yaneda
  • Patent number: 12082449
    Abstract: A separation wall is provided in a frame shape along a circumferential edge of a through-hole in a non-display region, in which the through-hole is formed, defined in an island shape inside a display region. The separation wall includes a wall base portion provided in a frame shape by a part of a second interlayer insulating film and a resin layer provided in an eave shape on the wall base portion to extend to a through-hole side and a display region side. Opening portions opening upward are provided on peripheries of the wall base portion on the through-hole side and the display region side in the second interlayer insulating film.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: September 3, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinsuke Saida, Shinji Ichikawa, Ryosuke Gunji, Tohru Okabe, Akira Inoue, Yoshihiro Nakada, Hiroharu Jinmura
  • Patent number: 11997889
    Abstract: Frame wiring lines are provided in a frame region, a flattening film in which a frame-shaped slit is formed in the frame region is provided in the display region and the frame region, a plurality of first electrodes constituting light-emitting elements are provided on the flattening film, and conductive layer made of the same material and formed in the same layer as those of each of the plurality of first electrodes are provided covering at least end faces of the frame wiring lines exposed from the slit.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 28, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroki Taniyama, Ryosuke Gunji, Shinsuke Saida, Shinji Ichikawa, Tohru Okabe, Kohji Ariga, Akira Inoue, Yoshihiro Kohara, Koji Tanimura, Yoshihiro Nakada, Hiroharu Jinmura
  • Publication number: 20240164151
    Abstract: Provided is the following: a resin substrate layer; a thin-film transistor layer provided on the resin substrate layer, and having a stack of, in sequence, a gate insulating film, an interlayer insulating film, and a flattening film; and a light-emitting element layer provided on the thin-film transistor layer, with a plurality of first electrodes, a common edge cover that is common, a plurality of light-emitting function layers, and a second electrode that is common being stacked sequentially in correspondence with a plurality of subpixels constituting a display region. A non-display region that is in the form of an island within the display region has a through-hole. The non-display region includes a first light-blocking film provided on the periphery of the flattening film so as to cover the side wall of the periphery.
    Type: Application
    Filed: March 31, 2021
    Publication date: May 16, 2024
    Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
  • Publication number: 20240147789
    Abstract: A display device, includes: a base substrate layer; a thin-film transistor layer provided on the base substrate layer, and including a plurality of subpixels forming a display region, each of the subpixels being provided with a thin-film transistor on which a planarization film is stacked; and a light-emitting element layer provided on the thin-film transistor layer, and including a plurality of first electrodes, a common edge cover, a plurality of light-emitting functional layers, and a common second electrode, all of which are sequentially stacked on top of another in association with the plurality of subpixels, wherein each of the first electrodes has a peripheral edge portion provided to: surround, in plan view, the thin-film transistor corresponding to the first electrode; and protrude toward the base substrate layer.
    Type: Application
    Filed: April 27, 2021
    Publication date: May 2, 2024
    Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
  • Patent number: 11968861
    Abstract: An organic EL display (1) has a bend (B) where a slit (81) is bored in a base coat film (23), gate insulating film (27), first interlayer insulating film (31) and second interlayer insulating film (35). The bend is provided with a filler layer (83) filling the slit and covering both edges of the slit. The filler layer has a protrusion (85) overlapping each edge in the width direction of the slit. A routed wire (7) routed from the display region (D) and then routed over the filler layer to reach a terminal section (T) extends over the protrusion.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: April 23, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Ichikawa, Shinsuke Saida, Ryosuke Gunji, Hiroki Taniyama, Tohru Okabe, Akira Inoue, Hiroharu Jinmura, Yoshihiro Nakada, Koji Tanimura
  • Patent number: 11957015
    Abstract: A lead wiring line is provided in a frame region to extend therein while intersecting with a frame-shaped dam wall, is formed of a same material and in a same layer as each of a plurality of display wiring lines in which a first metal layer, a second metal layer, and a third metal layer are layered in sequence, is electrically connected to the plurality of display wiring lines on a display region side, and is electrically connected to a terminal on a terminal portion side. The third metal layer is provided to cover a side surface of the first metal layer, and a side surface and an upper face of the second metal layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 9, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Takeshi Yaneda
  • Patent number: 11957014
    Abstract: A display device includes: a plurality of control lines; a plurality of power supply lines; a plurality of data signal lines; an oxide semiconductor layer; a first metal layer; a gate insulation film; a first inorganic insulation film; a second metal layer; a second inorganic insulation film; and a third metal layer. The oxide semiconductor layer, in a plan view, contains therein semiconductor lines formed as isolated regions between a plurality of drivers and a display area. The semiconductor lines cross the plurality of control lines and the plurality of power supply lines, are in contact with the plurality of control lines via an opening in a gate insulation film, are in contact with the plurality of power supply lines via an opening in the first inorganic insulation film, and have a plurality of narrowed portions, such that thicker and thinner regions exist along the same line.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 9, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Hiroharu Jinmura, Akira Inoue