Abstract: Provided is a semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a collector region of a second conductivity type provided on a back surface of the semiconductor substrate; a cathode region of the first conductivity type provided on the back surface of the semiconductor substrate and having a higher doping concentration than the drift region; a plurality of trench portions provided on a front surface of the semiconductor substrate; and a lifetime control portion provided in the semiconductor substrate and containing a lifetime killer, in which the lifetime control portion includes: a main region provided in a diode portion; and a decay region provided to extend from the main region in a direction parallel to the front surface of the semiconductor substrate and having a lifetime killer concentration that has decayed more than a lifetime killer concentration of the main region.

Abstract: Provided is a semiconductor device including: a collector region of a second conductivity type, which is provided between a drift region and a lower surface of a semiconductor substrate, in which the collector region includes a first region and a second region having a lower implantation efficiency of carriers with respect to the drift region than the first region, and when an area of the first region and an area of the second region per unit area of the collector region in a top view are respectively represented by S1 and S2, the implantation efficiency of the first region is represented by ?1, and the implantation efficiency of the second region is represented by ?2, an average implantation efficiency ?C given by an expression below is 0.1 or more and 0.4 or less: ?C=(S1×?1+S2×?2)/(S1+S2).

Abstract: A device includes a substrate with upper/lower surfaces, including hydrogen containing region having hydrogen chemical concentration peaks in a depth direction. A carrier concentration distribution of the hydrogen containing region includes a first carrier concentration peak, a second carrier concentration peak closest to the first carrier concentration peak, a third carrier concentration peak arranged closer to the upper surface than the second carrier concentration peak, a first inter peak region arranged between the first and second carrier concentration peaks, a second inter peak region arranged between the second and third carrier concentration peaks, and an inter-peaks concentration peak arranged in the second inter peak region such that the concentration peak does not overlap the hydrogen chemical concentration peaks in the second and third carrier concentration peaks. A local minimum value of a carrier concentration in the first inter peak region is smaller than that of the second inter peak region.

Abstract: Provided is a semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion. The device may include a first conductivity type drift region provided in a semiconductor substrate, a second conductivity type base region provided above the drift region, a first conductivity type emitter region provided above the base region and having a doping concentration higher than that of the drift region, and a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region. The contact region includes a first contact portion provided on a front surface of the substrate, and a second contact portion having a doping concentration different from that of the first contact portion and provided alternately with the first contact portion in a trench extending direction on a side wall of the first trench portion.

Abstract: Provided is a semiconductor device comprising a semiconductor substrate, wherein the semiconductor substrate includes a hydrogen containing region including hydrogen, and the hydrogen containing region includes a high concentration region with a higher carrier concentration than a virtual carrier concentration determined based on a concentration of hydrogen included and an activation ratio of hydrogen. The semiconductor substrate includes an N type drift region, an N type emitter region that has a higher carrier concentration than that in the drift region, a P type base region, a P type collector region provided to be in contact with a lower surface of the semiconductor substrate, and an N type buffer region that is provided between the collector region and the drift region, and has a higher carrier concentration than that in the drift region, and the hydrogen containing region is included in the buffer region.

Abstract: An active region has first and second cell regions respectively disposed in a main IGBT and a sensing IGBT. The second cell region has a detecting region in which the sensing IGBT is disposed and an extracting region that surrounds a periphery of the detecting region. A resistance region containing polysilicon and connected to the sensing IGBT is provided on the semiconductor substrate, in the extracting region. The resistance region connected to the sensing IGBT has a first portion connected to the gate electrodes of the sensing IGBT and a second portion connecting the first portion to the gate runner, and configures a built-in resistance of the second portion having a resistance value in a range from 10? to 5000?. As a result, a trade-off relationship between enhancing ESD tolerance of a current sensing region that includes the sensing IGBT and reducing transient sensing voltage may be improved.

Abstract: Provided is a semiconductor device comprising an active region and an edge region, the semiconductor device comprising: a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first collector region of the second conductivity type provided below the drift region in the active region; and a second collector region of the second conductivity type provided below the drift region in the edge region, wherein a doping concentration of the first collector region is higher than a doping concentration of the second collector region, wherein an area of the first collector region is of the same size as an area of the second collector region or larger than the area of the second collector region, in a top plan view.

Abstract: Provided is a semiconductor device that includes a semiconductor substrate that is provided with a first conductivity type drift region, a transistor portion that includes a second conductivity type collector region in contact with a lower surface of the semiconductor substrate, and a diode portion that includes a first conductivity type cathode region in contact with the lower surface of the semiconductor substrate, and is alternately disposed with the transistor portion along an arrangement direction in an upper surface of the semiconductor substrate. In the transistor portions, a width in the arrangement direction of two or more transistor portions sequentially selected from the transistor portions nearer to the center in the arrangement direction of the semiconductor substrate is larger than a width in the arrangement direction of one of the other transistor portions.

Abstract: There is provided a semiconductor device including: a pad portion that is provided above the upper surface of the semiconductor substrate and that is separated from the emitter electrode; a wire wiring portion that is connected to a connection region on an upper surface of the pad portion; a wiring layer that is provided between the semiconductor substrate and the pad portion and that includes a region overlapping the connection region; an interlayer dielectric film that is provided between the wiring layer and the pad portion and that has a through hole below the connection region; a tungsten portion that contains tungsten and that is provided inside the through hole and electrically connects the wiring layer and the pad portion; and a barrier metal layer that contains titanium and that is provided to cover an upper surface of the interlayer dielectric film below the connection region.

Abstract: There is provided a semiconductor device including a semiconductor substrate, the semiconductor device including: a sensing portion that is provided on the semiconductor substrate and that is configured to detect predetermined physical information; a sensing pad portion that is provided above an upper surface of the semiconductor substrate and that is connected to the sensing portion; a gate runner which is provided above the upper surface of the semiconductor substrate and to which a gate potential is applied; and one or more separated conductive portions in which each separated conductive portion is provided between the sensing pad portion and the semiconductor substrate and that is separated from the gate runner.

Abstract: A semiconductor device is an IGBT of a trench-gate structure and has a storage region directly beneath a p?-type base region. The semiconductor device has gate trenches and dummy trenches as trenches configuring the trench-gate structure. An interval (mesa width) at which the trenches are disposed is in a range of 0.7 ?m to 2 ?m. In each of the gate trenches, a gate electrode of a gate potential is provided via a first gate insulating film. In each of the dummy trenches, a dummy gate electrode of an emitter potential is provided via a second gate insulating film. A total number of the gate electrode is in a range of 60% to 84% of a total number of the dummy electrodes.

Abstract: A semiconductor device, including, a drift region of a first conductivity type provided on a semiconductor substrate; a field stop region of a first conductivity type provided below the drift region and having one or more peaks; and a collector region of a second conductivity type provided below the field stop region, wherein when an integral concentration of the collector region is set to be x [cm?2], a depth of a first peak that is a shallowest from the back surface of the semiconductor substrate out of the one or more peaks is set to be y1 [?m], line A1: y1=(?7.4699E?01)ln(x)+(2.7810E+01), and line B1: y1=(?4.7772E?01)ln(x)+(1.7960E+01), a depth of the first peak and the integral concentration are within a range between a line A1 and a line B1, is provided.

Abstract: A semiconductor device is an IGBT of a trench-gate structure and has a storage region directly beneath a p?-type base region. The semiconductor device has gate trenches and dummy trenches as trenches configuring the trench-gate structure. An interval (mesa width) at which the trenches are disposed is in a range of 0.7 ?m to 2 ?m. In each of the gate trenches, a gate electrode of a gate potential is provided via a first gate insulating film. In each of the dummy trenches, a dummy gate electrode of an emitter potential is provided via a second gate insulating film. A total number of the gate electrode is in a range of 60% to 84% of a total number of the dummy electrodes.

Abstract: Provided is a semiconductor device including a semiconductor substrate including a transistor portion and a diode portion. The semiconductor substrate includes a drift region of a first conductivity type provided inside. The transistor portion includes: a transistor region separated from the diode portion in a top view of the semiconductor substrate; and a boundary region located between the transistor region and the diode portion in a top view of the semiconductor substrate and including a lifetime control region on a front surface side of the semiconductor substrate in the drift region. The boundary region has a current suppression structure.

Abstract: To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region.

Abstract: To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region.

Abstract: Provided is a semiconductor device which includes a semiconductor substrate including a transistor portion and a diode portion. The transistor portion includes an injection suppression region that suppresses injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate. Both the transistor portion and the diode portion include a base region of a second conductivity type on a front surface of the semiconductor substrate, the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region on the front surface of the semiconductor substrate, and the injection suppression region is not provided with the emitter region and the extraction region.

Abstract: Provided is a semiconductor device which includes a semiconductor substrate including a transistor portion and a diode portion. The transistor portion includes an injection suppression region that suppresses injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate. The diode portion includes a lifetime control region including a lifetime killer. Both the transistor portion and the diode portion include a base region of a second conductivity type on a surface of the semiconductor substrate, the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region on the surface of the semiconductor substrate, and the injection suppression region is not provided with the emitter region and the extraction region.

Abstract: To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.

Abstract: Provided is a semiconductor device including a semiconductor substrate provided with a transistor portion, wherein the semiconductor substrate includes, in the transistor portion, a drift region of a first conductivity type; an accumulation region of the first conductivity type that has a higher doping concentration than the drift region; a collector region of a second conductivity type; and a plurality of gate trench portions and a plurality of dummy trench portions that are provided extending in a predetermined extension direction in the top surface of the semiconductor substrate, and are arranged in an arrangement direction orthogonal to the extension direction, and the transistor portion includes a first region that includes a gate trench portion; and a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region.