Abstract: Provided is a semiconductor device including a semiconductor substrate provided with a transistor portion, wherein the semiconductor substrate includes, in the transistor portion, a drift region of a first conductivity type; an accumulation region of the first conductivity type that has a higher doping concentration than the drift region; a collector region of a second conductivity type; and a plurality of gate trench portions and a plurality of dummy trench portions that are provided extending in a predetermined extension direction in the top surface of the semiconductor substrate, and are arranged in an arrangement direction orthogonal to the extension direction, and the transistor portion includes a first region that includes a gate trench portion; and a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region.

Abstract: Provided is a semiconductor device comprising an active region and an edge region, the semiconductor device comprising: a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first collector region of the second conductivity type provided below the drift region in the active region; and a second collector region of the second conductivity type provided below the drift region in the edge region, wherein a doping concentration of the first collector region is higher than a doping concentration of the second collector region, wherein an area of the first collector region is of the same size as an area of the second collector region or larger than the area of the second collector region, in a top plan view.

Abstract: To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.

Abstract: An active region has first and second cell regions respectively disposed in a main IGBT and a sensing IGBT. The second cell region has a detecting region in which the sensing IGBT is disposed and an extracting region that surrounds a periphery of the detecting region. A resistance region containing polysilicon and connected to the sensing IGBT is provided on the semiconductor substrate, in the extracting region. The resistance region connected to the sensing IGBT has a first portion connected to the gate electrodes of the sensing IGBT and a second portion connecting the first portion to the gate runner, and configures a built-in resistance of the second portion having a resistance value in a range from 10? to 5000?. As a result, a trade-off relationship between enhancing ESD tolerance of a current sensing region that includes the sensing IGBT and reducing transient sensing voltage may be improved.

Abstract: Provided is a semiconductor device that includes a semiconductor substrate that is provided with a first conductivity type drift region, a transistor portion that includes a second conductivity type collector region in contact with a lower surface of the semiconductor substrate, and a diode portion that includes a first conductivity type cathode region in contact with the lower surface of the semiconductor substrate, and is alternately disposed with the transistor portion along an arrangement direction in an upper surface of the semiconductor substrate. In the transistor portions, a width in the arrangement direction of two or more transistor portions sequentially selected from the transistor portions nearer to the center in the arrangement direction of the semiconductor substrate is larger than a width in the arrangement direction of one of the other transistor portions.

Abstract: Provided is a semiconductor device comprising a semiconductor substrate, wherein the semiconductor substrate includes a hydrogen containing region including hydrogen, and the hydrogen containing region includes a high concentration region with a higher carrier concentration than a virtual carrier concentration determined based on a concentration of hydrogen included and an activation ratio of hydrogen. The semiconductor substrate includes an N type drift region, an N type emitter region that has a higher carrier concentration than that in the drift region, a P type base region, a P type collector region provided to be in contact with a lower surface of the semiconductor substrate, and an N type buffer region that is provided between the collector region and the drift region, and has a higher carrier concentration than that in the drift region, and the hydrogen containing region is included in the buffer region.

Abstract: Provided is a semiconductor device including a semiconductor substrate provided with a transistor portion, wherein the semiconductor substrate includes, in the transistor portion, a drift region of a first conductivity type; an accumulation region of the first conductivity type that has a higher doping concentration than the drift region; a collector region of a second conductivity type; and a plurality of gate trench portions and a plurality of dummy trench portions that are provided extending in a predetermined extension direction in the top surface of the semiconductor substrate, and are arranged in an arrangement direction orthogonal to the extension direction, and the transistor portion includes a first region that includes a gate trench portion; and a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region.

Abstract: A semiconductor device includes a transistor portion which includes a plurality of gate structure portions, and a diode portion which includes a cathode region in a lower surface of a semiconductor substrate. Each of the gate structure portions includes a gate trench portion, an emitter region of a first conductive type which is provided between an upper surface of the semiconductor substrate and a drift region to abut on the gate trench portion, and a base region of a second conductive type which is provided between the emitter region and the drift region to abut on the gate trench portion. A first threshold of the gate structure portion with a shortest distance to the cathode region in a top view is lower than a second threshold of the gate structure portion with a longest distance to the cathode region by 0.1 V or more and 1 V or less.

Abstract: An IGBT region in which an IGBT is disposed and a FWD region in which a FWD connected in antiparallel to the IGBT is disposed are provided in an active region of a semiconductor chip. In the active region, the FWD region is provided in plural separated from each other. The IGBT region is a continuous region between the FWD regions. In the IGBT region and the FWD region, first and second gate trenches are disposed in striped-shape layouts that are parallel to a front surface of the semiconductor chip and extend along a same first direction. The second gate trenches of the FWDs of the FWD regions are disposed separated from the first gate trenches of the IGBT in the IGBT region. This structure enables degradation of element characteristics to be prevented, and heat dissipation of the semiconductor chip and the degrees of freedom in design to be enhanced.

Abstract: A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.

Abstract: A semiconductor device is an IGBT of a trench-gate structure and has a storage region directly beneath a p?-type base region. The semiconductor device has gate trenches and dummy trenches as trenches configuring the trench-gate structure. An interval (mesa width) at which the trenches are disposed is in a range of 0.7 ?m to 2 ?m. In each of the gate trenches, a gate electrode of a gate potential is provided via a first gate insulating film. In each of the dummy trenches, a dummy gate electrode of an emitter potential is provided via a second gate insulating film. A total number of the gate electrode is in a range of 60% to 84% of a total number of the dummy electrodes.

Abstract: In an edge termination region, in a carrier drawing region between an active region and a gate runner part, a p+-type contact region is provided in a surface region of a p-type well region. In the carrier drawing region, in second contact holes formed an interlayer insulating film, a contact plug is embedded in each via the barrier metal, and contacts of the p+-type contact region and the barrier metal at an emitter electric potential are formed. The contacts of the carrier drawing region are disposed in a striped layout extending along an outer periphery of the active region; the contacts surround the active region. A contact resistance of the contacts of the carrier drawing region is higher than a contact resistance of a contact (emitter contact) of a MOS gate.

Abstract: To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region.

Abstract: An IGBT includes current sense cell having a sensing area for sensing a current flowing an active area and an extraction area for extracting a hole current. The extraction area around the sensing area, has a portion in a gate trench is not in contact with the emitter region, and a p-type well region provided deeper than the first trench and having a high impurity concentration. An area of the extraction area is four times or more and 10,000 times or less an area of the sensing area.

Abstract: To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.

Abstract: A super junction MOSFET device including a semiconductor substrate; a base region provided on a primary surface side of the semiconductor substrate and having impurities of a first conductivity type; a source region that includes a portion of a frontmost surface of the base region and has impurities of a second conductivity type; a gate electrode that penetrates through the base region; a source electrode that is provided on the base region and is electrically connected to the source region; and a front surface region that is provided on an entirety of the frontmost surface of the base region in a region differing from a region where the source region and the gate electrode are provided in the base region, is electrically connected to the source electrode provided on the base region, and has a lower impurity concentration of impurities of the second conductivity type than the source region.

Abstract: A semiconductor device including: a semiconductor substrate having a drift region of the first conductivity type; a cathode region formed on the lower surface of the semiconductor substrate; a diode portion having the cathode region formed on the lower surface of the semiconductor substrate; the first dummy trench portion provided from the upper surface of the semiconductor substrate to the drift region, including one part provided inside the diode portion and the other part provided outside the diode portion, and provided extending in series from inside the diode portion to outside the diode portion in a predetermined extending direction on the upper surface of the semiconductor substrate; and the first lead-out portion that is provided on the upper surface of the semiconductor substrate, and electrically connected to the first dummy trench portion outside the diode portion is provided.

Abstract: An IGBT region in which an IGBT is disposed and a FWD region in which a FWD connected in antiparallel to the IGBT is disposed are provided in an active region of a semiconductor chip. In the active region, the FWD region is provided in plural separated from each other. The IGBT region is a continuous region between the FWD regions. In the IGBT region and the FWD region, first and second gate trenches are disposed in striped-shape layouts that are parallel to a front surface of the semiconductor chip and extend along a same first direction. The second gate trenches of the FWDs of the FWD regions are disposed separated from the first gate trenches of the IGBT in the IGBT region. This structure enables degradation of element characteristics to be prevented, and heat dissipation of the semiconductor chip and the degrees of freedom in design to be enhanced.

Abstract: A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.

Abstract: An IGBT includes current sense cell having a sensing area for sensing a current flowing an active area and an extraction area for extracting a hole current. The extraction area around the sensing area, has a portion in a gate trench is not in contact with the emitter region, and a p-type well region provided deeper than the first trench and having a high impurity concentration. An area of the extraction area is four times or more and 10,000 times or less an area of the sensing area.