Abstract: A super junction MOSFET device including a semiconductor substrate; a base region provided on a primary surface side of the semiconductor substrate and having impurities of a first conductivity type; a source region that includes a portion of a frontmost surface of the base region and has impurities of a second conductivity type; a gate electrode that penetrates through the base region; a source electrode that is provided on the base region and is electrically connected to the source region; and a front surface region that is provided on an entirety of the frontmost surface of the base region in a region differing from a region where the source region and the gate electrode are provided in the base region, is electrically connected to the source electrode provided on the base region, and has a lower impurity concentration of impurities of the second conductivity type than the source region.

Abstract: A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.

Abstract: A semiconductor device including: a semiconductor substrate having a drift region of the first conductivity type; a cathode region formed on the lower surface of the semiconductor substrate; a diode portion having the cathode region formed on the lower surface of the semiconductor substrate; the first dummy trench portion provided from the upper surface of the semiconductor substrate to the drift region, including one part provided inside the diode portion and the other part provided outside the diode portion, and provided extending in series from inside the diode portion to outside the diode portion in a predetermined extending direction on the upper surface of the semiconductor substrate; and the first lead-out portion that is provided on the upper surface of the semiconductor substrate, and electrically connected to the first dummy trench portion outside the diode portion is provided.

Abstract: In an edge termination region, in a carrier drawing region between an active region and a gate runner part, a p+-type contact region is provided in a surface region of a p-type well region. In the carrier drawing region, in second contact holes formed an interlayer insulating film, a contact plug is embedded in each via the barrier metal, and contacts of the p+-type contact region and the barrier metal at an emitter electric potential are formed. The contacts of the carrier drawing region are disposed in a striped layout extending along an outer periphery of the active region; the contacts surround the active region. A contact resistance of the contacts of the carrier drawing region is higher than a contact resistance of a contact (emitter contact) of a MOS gate.

Abstract: A super junction MOSFET device including a semiconductor substrate; a base region provided on a primary surface side of the semiconductor substrate and having impurities of a first conductivity type; a source region that includes a portion of a frontmost surface of the base region and has impurities of a second conductivity type; a gate electrode that penetrates through the base region; a source electrode that is provided on the base region and is electrically connected to the source region; and a front surface region that is provided on an entirety of the frontmost surface of the base region in a region differing from a region where the source region and the gate electrode are provided in the base region, is electrically connected to the source electrode provided on the base region, and has a lower impurity concentration of impurities of the second conductivity type than the source region.

Abstract: An RC-IGBT has a chip area of the semiconductor chip larger than that of a semiconductor chip including an IGBT section but not including an FWD section, as it is provided with the FWD section. It is demanded to reduce the chip area of the RC-IGBT semiconductor chip. Provided is a semiconductor device including: a transistor section including a plurality of transistors; a free wheeling diode section being at least opposite to one side of the transistor section and provided outside the transistor section, when the transistor section is seen from a top view; and a gate runner section and a gate pad section provided to contact the transistor section and not surrounding an entire periphery of the transistor section, when the transistor section is seen from a top view.

Abstract: To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.

Abstract: A semiconductor device for driving a load includes: a protection circuit configured to be connected to the load, the protection circuit including a protection diode, a diode-connected unipolar protection element, and a diode-connected bipolar protection element, all of which are connected in parallel so that when connected to the load, the protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in parallel to the load; and a switching circuit that is connected in series to the protection circuit and that performs a switching operation so as to drive the load. The protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in such a polarity that each is reverse-biased when the switching circuit is turned ON, and consume a discharge current resulting from a counter-electromotive force from the load when the switching circuit is turned OFF.

Abstract: An RC-IGBT has a chip area of the semiconductor chip larger than that of a semiconductor chip including an IGBT section but not including an FWD section, as it is provided with the FWD section. It is demanded to reduce the chip area of the RC-IGBT semiconductor chip. Provided is a semiconductor device including: a transistor section including a plurality of transistors; a free wheeling diode section being at least opposite to one side of the transistor section and provided outside the transistor section, when the transistor section is seen from a top view; and a gate runner section and a gate pad section provided to contact the transistor section and not surrounding an entire periphery of the transistor section, when the transistor section is seen from a top view.

Abstract: To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.

Abstract: A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.

Abstract: A super junction MOSFET device including a semiconductor substrate; a base region provided on a primary surface side of the semiconductor substrate and having impurities of a first conductivity type; a source region that includes a portion of a frontmost surface of the base region and has impurities of a second conductivity type; a gate electrode that penetrates through the base region; a source electrode that is provided on the base region and is electrically connected to the source region; and a front surface region that is provided on an entirety of the frontmost surface of the base region in a region differing from a region where the source region and the gate electrode are provided in the base region, is electrically connected to the source electrode provided on the base region, and has a lower impurity concentration of impurities of the second conductivity type than the source region.

Abstract: A semiconductor device for driving a load includes: a protection circuit configured to be connected to the load, the protection circuit including a protection diode, a diode-connected unipolar protection element, and a diode-connected bipolar protection element, all of which are connected in parallel so that when connected to the load, the protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in parallel to the load; and a switching circuit that is connected in series to the protection circuit and that performs a switching operation so as to drive the load. The protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in such a polarity that each is reverse-biased when the switching circuit is turned ON, and consume a discharge current resulting from a counter-electromotive force from the load when the switching circuit is turned OFF.