Abstract: An adaptive blocking coding system selects an effective blocking of an input image signal to be encoded in accordance with the correlation between fields, even if motion is detected between the fields. The blocking patterns include an individual field blocking, a non-interlace blocking, a split blocking and an inverted split blocking. Further, the coding system searches for motion from both odd and even fields of a frame for producing a motion compensated prediction signal in order to provide high-efficiency coding.

Abstract: An image coding system determines an amount a data that is output by a coder of the system and also determines a target code produced amount based on the motion of an input image. The coder of the coding system encodes the input image. A record of a data amount of past coded data is used as the inference of the target code amount. Hence, proper coding can be performed in a sending side. Further, by converting the data amount into a value with a condition to be standard, accuracy of the inference may be improved. In addition, an indication of the power amount of the data to be coded is used as a factor for determining a target code produced amount to expedite a combination of a plurality of coding modes.

Abstract: A digital signal processor having a data decision device for selecting an output from one of an arithmetic calculator within a calculating unit, a logical shifter or a multiplier in parallel with the calculating unit. The data decision device simultaneously compares in parallel selected output data with n-threshold values defining (n+1) data regions for determining in which region among the (n+1) data regions the output data exists. The resultant region in which the output data is determined to exist is compared with m region limiting conditions to output either branch address information when coincidence is found to exist or a signal representative of incoincidence when all of the m conditions are incoincident.

Abstract: An image coding system determines an amount a data that is output by a coder of the system and also determines a target code produced amount based on the motion of an input image. The coder of the coding system encodes the input image. A record of a data amount of past coded data is used as the inference of the target code amount. Hence, proper coding can be performed in a sending side. Further, by converting the data amount into a value with a condition to be standard, accuracy of the inference may be improved. In addition, an indication of the power amount of the data to be coded is used as a factor for determining a target code produced amount to expedite a combination of a plurality of coding modes.

Abstract: A vector quantizer which transmits the input vector of the time when the minimum distortion is larger than the preset distortion threshold value and stores such input vector into the second code book as the new quantizing representative vector for the use in the successive vector quantizing processes.Further, since the first and second code book constitute in the form of tree-structure, calculation for search may be executed at a high speed.

Abstract: An adaptive blocking coding system selects an effective blocking of an input image signal to be encoded in accordance with the correlation between fields, even if motion is detected between the fields. The blocking patterns include an individual field blocking, a non-interlace blocking, a split blocking and an inverted split blocking. Further, the coding system searches for motion from both odd and even fields of a frame for producing a motion compensated prediction signal in order to provide high-efficiency coding.

Abstract: An encoding/decoding apparatus is described wherein an encoding apparatus comprises a feature-image-extracting section, a three-dimensional shape model adjustment section, a brightness information detection section, a patch dividing section and a threshold processing section, and a decoding apparatus comprises a three-dimensional shape model forming section and a synthesizing section. Feature image information extracted from input signals by the extracting section is adjusted with three-dimensional shape basic model information by the adjustment section and then a brightness diffusion value for each triangle patch constituting the adjusted three-dimensional shape model is detected by the detection section.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: An encoding/decoding apparatus is described wherein an encoding apparatus comprises a feature-image-extracting section, a three-dimensional shape model adjustment section, a brightness information detection section, a patch dividing section and a threshold processing section, and a decoding apparatus comprises a three-dimensional shape model forming section and a synthesizing section. Feature image information extracted from input signals by the extracting section is adjusted with three-dimensional shape basic model information by the adjustment section and then a brightness diffusion value for each triangle patch constituting the adjusted three-dimensional shape model is detected by the detection section.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A coding controller takes a buffer occupancy at present from a transmission buffer, and a first normalized value evaluating device outputs a first normalized value, independent of a video rate. A frame rate for the number of bits per block (n.times.QB) is determined and a second normalized value evaluating device outputs a second normalized value for the number of bits per one frame. When the number of bits is relatively small, a second quantization characteristics control table is selected in a selector and the coding control is performed every frame. When the number of bits is large, a first quantization characteristics control table is selected in the selector and the control is performed every block (n.times.QB), instead of the control every frame. The quantization characteristics control signal is then outputted.

Abstract: A vector quantizer which transmits the input vector of the time when the minimum distortion is larger than the preset distortion threshold value and stores such input vector into the second code book as the new quantizing representative vector for the use in the successive vector quantizing processes. Further, since the first and second code book constitute in the form of tree-structure, calculation for search may be executed at a high speed.

Abstract: An apparatus for decoding a received BCH code signal for correcting a combined complex error is disclosed which includes a syndrome generating circuit for generating two n-bit syndromes corresponding to the received signal, a syndrome converting circuit for converting the two n-bit syndromes to a 2n-bit syndrome, a random error correcting circuit, a burst error correcting circuit, two combining circuits and output selecting circuit. The random error correcting circuit receives input as the two n-bit syndromes and outputs a random error correction signal to one of the combining circuits and the burst error correcting circuit receives as input the 2n-bit syndrome and outputs a burst error correction signal to the other of the combining circuits. The combining circuits combine the correction signals with the received BCH code signal.

Abstract: The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reducing a required amount of calculations when an amount of distortion between a last frame block and a current frame block; in processing a direct memory access at a higher efficiency; in processing a subdivided data calculation at a higher speed; in processing a branch instruction occurring in the pipeline process at a higher efficiency; and in processing an interruption occurring in a repeat process operation at greater convenience, and furthermore in reducing a required amount of calculations through minimum distortion searching processes hierarchized.

Abstract: A digital signal processing apparatus which is used for the computation of coding image signals or the like and a motion compensative operation method which uses a digital signal processing apparatus. The apparatus comprises a plurality of signal processing means arranged in parallel and control means which assigns loads to the signal processing means so that the signal processing means have even computation volumes. Alternatively, an address generator is provided for each of data sets entered independently. An intermediate check is conducted during the computation for a block which involves a motion compensative operation.

Abstract: A video codec system inputs consecutively frame after frame of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each piece of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.

Abstract: An amplitude-adaptive vector quantization system intended for efficient signal coding and decoding. A mean value separation circuit (2) separates the mean value from an input signal which has been divided into blocks, and a tree-search vector quantizer (6) implements tree-search inner product vector quantization so that index information is truncated depending on the detected vector amplitude, thereby reducing the volume of information for transmission.

Abstract: A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.