Abstract: A TFT circuit (101) includes a first node (N1) to which a first low potential (Vc) is supplied, a depression-type first TFT (21) which is arranged between the first node (N1) and low-potential wiring (11) for supplying a second low potential (Va) higher than the first low potential (Vc), and in which a drain terminal is connected to the first node, and a depression-type second TFT (22) which is arranged between the first TFT (21) and the low potential wiring (11) and in which a source terminal is connected to a source terminal of the first TFT, in which the first low potential (Vc) is supplied to a gate terminal of the second TFT, a second node (N2) enterable a floating state is formed between the source terminal of the first TFT and the source terminal of the second TFT, and the second node (N2) is connected to a sub-circuit (SC1) which is settable a potential of the second node (N2) to be lower than the second low potential (Va) and higher than the first low potential (Vc).

Abstract: A semiconductor device includes a circuit including a first TFT (101) which is an oxide semiconductor TFT, an inorganic insulating layer (11) covering the first TFT, a lower transparent electrode and an upper transparent electrode arranged with a dielectric layer (17) therebetween, and a shield layer (30) formed from the same transparent conductive film as the lower or upper transparent electrode, wherein: one of the lower and upper transparent electrodes is a common electrode; the shield layer (30) is electrically connected to the common electrode; the shield layer (30) includes a second gate electrode (BG) of the first TFT; and (a) the second gate electrode (BG) is arranged on the inorganic insulating layer so as to be in contact with an upper surface of the inorganic insulating layer, or (b) over a channel region of the first TFT, the dielectric layer (17) is in contact with the upper surface of the inorganic insulating layer (11), and the second gate electrode (BG) is arranged on the dielectric layer so a

Abstract: A magnetron sputtering device includes alternating current power supplies each connected to a first target and a second target in a pair, and a controller configured to control a phase difference between voltages output from the alternating current power supplies connected to the first targets and the second targets in the pairs adjacent to each other.

Abstract: Each of the auxiliary capacitors (6a) includes a capacitor line (11b) comprised of the same material as the gate electrode (11a) and provided in the same layer as the gate electrode (11a), the gate insulating film (12) provided so as to cover the capacitor line (11a), a capacitor intermediate layer (13c) provided using the oxide semiconductor and provided on the gate insulating film (12) so as to overlap the capacitor line (11b), and a capacitor electrode (15b) provided on the capacitor intermediate layer (13c), and the capacitor intermediate layer (13c) is conductive.

Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).

Abstract: A magnetron sputtering device includes alternating current power supplies each connected to a first target and a second target in a pair, and a controller configured to control a phase difference between voltages output from the alternating current power supplies connected to the first targets and the second targets in the pairs adjacent to each other.

Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).

Abstract: A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.

Abstract: A magnetron sputtering device is provided with: a target part positioned in such a manner as to face a substrate held by a substrate holding part; a power source that supplies power to the target part; a magnet part that moves back and forth along the rear of the target part; a chamber having side walls that are electrically grounded; and a power source control part that controls the power source in such a manner that, while the magnet part is away from approach points, which are points respectively closest to the side walls, a prescribed voltage is applied to the target part by the power source, but the prescribed voltage is reduced when the magnet part reaches one of the approach points.

Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).

Abstract: A TFT substrate (30a) including a TFT (5a) having: a gate electrode (14a) provided on a substrate (10a); a gate insulating film (15) provided to cover the gate electrode (14a); a semiconductor layer (16a) made of an oxide semiconductor provided on the gate insulating film (15) with a channel region (C) arranged to lie above the gate electrode (14a): and a source electrode (19aa) and a drain electrode (19b) provided on the semiconductor layer (16a) to be spaced from each other with the channel region (C) therebetween. A recess (R) is provided on the surface of the channel region (C) of the semiconductor layer (16a) to extend in the channel width direction.

Abstract: A semiconductor device 10 according to the present invention includes an active layer 14 supported on a substrate 11 and having two channel regions 14c1, 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1, 14c2; a contact layer 16 having a source contact region 16s, a drain contact region 16d, and an intermediate contact region 16m; a source electrode 18s; a drain electrode 18d; an intermediate electrode 18m; and a gate electrode 12 facing the two channel regions and the intermediate region through a gate insulating film 13 interposed therebetween. An entire portion of the intermediate electrode 18m that is located between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13.

Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).

Abstract: A display device includes a plurality of spacer rows that are provided outside a display region on one of a pair of substrates, and each of the spacer rows is defined by a plurality of spacers arranged in a row at predetermined intervals along an outer edge of the display region. Each spacer has a substantially elongated shape extending along the outer edge of the display region. A gap between adjacent spacers in each spacer row is defined by a slit portion having a shorter length than a longitudinal length of the spacer, and the plurality of spacer rows are entirely covered by the seal member between the pair of substrates.

Abstract: In a method for manufacturing a liquid crystal display panel, a sealant having a cut-out formed at least on the other end side of a display region is provided on one film substrate. A liquid crystal material is supplied to one end side of the display region in the one film substrate or the other film substrate. An apparatus for manufacturing a liquid crystal display panel includes a bonding unit arranged to bond the pair of film substrates and to each other through the sealant and the liquid crystal material by pressing respective surfaces of the film substrates and so that a pressure in a middle of the film substrates and becomes higher than that at both ends thereof, and a sealing unit arranged to seal the cut-out of the sealant to the pair of film substrates and bonded in the bonding unit.

Abstract: A liquid crystal display panel manufacturing apparatus for successively bonding a pair of film substrates, each having a plurality of display regions defined at least along a longitudinal direction, along the longitudinal direction through a sealant formed in every display region of one of the film substrates includes: a first processing unit arranged to form a bonded body by bonding the film substrates so that the respective display regions are superimposed on each other; and a second processing unit including a molding roll configured to hold the bonded body formed in the first processing unit onto a peripheral wall thereof, and arranged to mold the bonded body into a curved shape along the peripheral wall of the molding roll by curing the sealant while holding the bonded body on the peripheral wall of the molding roll.

Abstract: The multilayer wiring board is provided with a lower layer wiring (8), and an upper layer wiring (10) formed on the lower layer wiring (8) through an interlayer insulating layer (9). On the interlayer insulating layer (9), a contact hole (11) is provided for interconnecting the upper layer wiring (8) with the lower layer wiring (10). A region surrounded by an inner wall (13) which forms the contact hole (11) is permitted to have a linewidth region wherein a wide line region (13A) and protruding regions (13B, 13C) as regions having different linewidths are connected. Thus, film thickness distribution of an ink baked product (12) formed at the contact hole (11) rises at the protruding regions (13B, 13C), and highly reliable multilayer interconnection can be performed between the lower layer wiring (8) and the upper layer wiring (10).

Abstract: A semiconductor device 100 according to the present invention includes a TFT 120 and a TFT 140. The TFT 120 has a gate electrode 122, a semiconductor layer 130 including a microcrystalline semiconductor film 132, and a gate insulating layer 124 provided between the gate electrode 122 and the semiconductor layer 130. The TFT 140 has a gate electrode 142, a semiconductor layer 150 including a microcrystalline semiconductor film 152, and a gate insulating layer 144 provided between the gate electrode 142 and the semiconductor layer 150. The thickness and layer structure of the semiconductor layer 150 of the TFT 140 are different from those of the semiconductor layer 130 of the TFT 120.

Abstract: A shift register of at least one embodiment of the present invention is a shift register supported by an insulative substrate, wherein: the shift register includes a plurality of stages each sequentially outputting output signals; each of the plurality of stages includes a first transistor for outputting the output signals, and a plurality of second transistors whose source region or drain region is electrically connected to a gate electrode of the first transistor; and the plurality of second transistors include a multi-channel transistor having an active layer including at least two channel regions, a source region and a drain region. This improves characteristics of a shift register forming a monolithic gate driver.

Abstract: A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.