Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.

Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure different blocks of the plurality of blocks of memory cells in different configurations, which can include blocks configured to include only groups of user data memory cells for storing user data, blocks configured to include only groups of overhead data memory cells for storing error correction code (ECC) data, and blocks configured to include groups of user data memory cells and groups of overhead data memory cells.

Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of memory cells of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of memory cells of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of memory cells.

Abstract: A method for reading an array of memory cells includes enabling a current to flow through even data lines of the array of memory cells. The method includes blocking a current from flowing through odd data lines of the array of memory cells. The method includes sensing data stored in memory cells coupled to the even data lines.

Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.

Abstract: Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.

Abstract: Memory having an array of memory cells and configured to store a first value representative of a characteristic sensed from a first data line, store a second value representative of the characteristic sensed from a second data line, perform an operation on the first value and the data value at a first logic circuitry, and perform an operation on an output of the first logic circuitry and a threshold data value at a second logic circuitry.

Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.

Abstract: Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.

Abstract: Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.

Abstract: Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.

Abstract: Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.

Abstract: Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.

Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

Abstract: Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line.

Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.

Abstract: A method for reading an array of memory cells includes enabling a current to flow through even data lines of the array of memory cells. The method includes blocking a current from flowing through odd data lines of the array of memory cells. The method includes sensing data stored in memory cells coupled to the even data lines.