Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second conductive members, a semiconductor member, and a first insulating member. The first conductive member is electrically connected with the second electrode or is electrically connectable with the second electrode. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first to fourth partial regions. The third partial region is between the first and second partial regions. The second semiconductor region is between the third partial region and the third semiconductor region. The fourth partial region is between the third partial region and the second semiconductor region. At least a portion of the second semiconductor region is between the second conductive member and the third electrode. The second conductive member is electrically insulated from the second and third electrodes. The first insulating member includes first to third insulating regions.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor regions, a first member, and a first insulating member. A direction from the first electrode toward the second electrode is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the second partial region toward the first partial region crosses the first direction. The third partial region is between the second partial region and the second semiconductor region in the first direction. The third semiconductor region is provided between the third partial region and the second semiconductor region. The first insulating member includes a first insulating region and a second insulating region. The first insulating region is between the third partial region and the first member. The second insulating region is between the third semiconductor region and the third electrode.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other-end portion. The first conductive member includes a first conductive member end portion and a first conductive member other-end portion. The first conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is electrically connected with the second electrode. The fourth semiconductor region is electrically connected with the first electrode. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member.

Abstract: According to one embodiment, a semiconductor device includes first, second and third conductive parts, a first semiconductor region, and a first insulating part. A direction from the first conductive part toward the second conductive part is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes an opposing surface facing the second conductive part. A direction from the opposing surface toward the third conductive part is along the second direction. The first insulating part includes a first insulating region. At least a portion of the first insulating region is between the opposing surface and the third conductive part.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a conductive member, and an insulating member. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first and second partial regions. The second semiconductor region is between the first partial region and the third semiconductor region. The conductive member is located between the second partial region and the third electrode. The conductive member includes a first end portion and a first other-end portion. The first end portion is between the first other-end portion and the third electrode. The conductive member includes first to third portions. The second portion is between the third portion and the third electrode. The first portion is between the second portion and the third electrode. The first portion includes the first end portion. The second portion contacts the first and third portions.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a conductive member, a semiconductor member, and an insulating member. The second electrode includes a conductive portion. The conductive portion is between the third electrode and the conductive member. The conductive member is electrically connected with the second electrode. The semiconductor member includes first to third semiconductor regions. The second semiconductor region is between the third semiconductor region and a portion of the first semiconductor region. The second semiconductor region is between the third electrode and the conductive member. The conductive portion is electrically connected with the second and third semiconductor regions. The first electrode is electrically connected with the first semiconductor region. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member.

Abstract: According to one embodiment, a semiconductor device includes a supporter including a first surface, first, second, and third conductive parts, a semiconductor region, and an insulating part. A first direction from the first toward second conductive part is along the first surface. The semiconductor region includes first, second, and third partial regions. A second direction from the first toward second partial region is along the first surface and crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes a counter surface facing the second conductive part. A direction from the counter surface toward the third conductive part is along the second direction. The insulating part includes an insulating region. At least a portion of the insulating region is between the counter surface and the third conductive part.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, first and second electrodes, a gate electrode, a gate terminal, a first conductive member, a first terminal, and a first insulating member. The semiconductor member includes first and second semiconductor regions, and a third semiconductor region provided between the first and second semiconductor regions. The first electrode is electrically connected to the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The gate terminal is electrically connected to the gate electrode. The first conductive member is electrically insulated from the first and second electrodes, and the gate electrode. The first terminal is electrically connected to the first conductive member.

Abstract: According to one embodiment, a semiconductor device includes first, second, third semiconductor members, a first conductive member, a connection member, and an insulating member. The first electrode includes first, second, and third electrode regions. A direction from the first toward second electrode is along a first direction. The second electrode includes fourth, fifth, and sixth electrode regions. The first semiconductor member includes first, second, third, fourth, and fifth partial regions. The second semiconductor member includes first and second semiconductor regions. The third semiconductor member includes third and fourth semiconductor regions. The third electrode is provided between the third partial region and the sixth electrode region in the first direction. The connection member is electrically connected to the first conductive member and the second electrode. The insulating member includes first, second, third, fourth, and fifth portions.

Abstract: According to one embodiment, a semiconductor device includes first, second and third conductive parts, a first semiconductor region, and a first insulating part. A direction from the first conductive part toward the second conductive part is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes an opposing surface facing the second conductive part. A direction from the opposing surface toward the third conductive part is along the second direction. The first insulating part includes a first insulating region. At least a portion of the first insulating region is between the opposing surface and the third conductive part.

Abstract: A semiconductor device includes first and second electrode, a semiconductor part therebetween, and first and second control electrode. The first control electrode is provided in a first trench between the first electrode and the semiconductor part. The second control electrode is provided in a second trench between the second electrode and the semiconductor part. The semiconductor part includes first, third, fifth and sixth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The sixth layer is provided between the first layer and the second electrode. The second electrode is electrically connected to the first layer via a first-conductivity-region including the sixth layer.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor regions, a first member, and a first insulating member. A direction from the first electrode toward the second electrode is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the second partial region toward the first partial region crosses the first direction. The third partial region is between the second partial region and the second semiconductor region in the first direction. The third semiconductor region is provided between the third partial region and the second semiconductor region. The first insulating member includes a first insulating region and a second insulating region. The first insulating region is between the third partial region and the first member. The second insulating region is between the third semiconductor region and the third electrode.

Abstract: According to one embodiment, a semiconductor device includes first, and second conductive members, first, second, and third semiconductor regions, and an insulating part. A direction from the first conductive member toward the second conductive member is along a first direction. The first semiconductor region includes first and second partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The first conductive member is between the first partial region and the second conductive member. A direction from the second partial region toward the second semiconductor region is along the first direction. A direction from the second conductive member toward the second semiconductor region is along the second direction. The third semiconductor region is between the second partial region and the second semiconductor region. The insulating part includes a first insulating region, a second insulating region, and a third insulating region.

Abstract: A magnetic device includes: a first conductive layer; a first magnetoresistive effect element disposed on the first conductive layer and including a first control terminal; and a first circuit configured to supply a first current in a first direction into the first conductive layer and apply a first control voltage to the first control terminal of the first magnetoresistive effect element, wherein in a case in which the first current is supplied to the first conductive layer, the first magnetoresistive effect element holds a value corresponding to a logical disjunction between a first value of first data in the first magnetoresistive effect element and a second value of the first control voltage corresponding to second data.

Abstract: A magnetic memory device includes a conductive member, a stacked body, and a controller. The stacked body includes a first magnetic layer, a second magnetic layer provided between the conductive member and the first magnetic layer, and a third magnetic layer stacked with the first magnetic layer and the second magnetic layer. The controller causes a current to flow in the conductive member. The controller causes a current to flow between the conductive member and the stacked body. The controller is able to identify three or more levels of an electrical resistance value of the stacked body.

Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.

Abstract: According to one embodiment, a magnetic memory device includes a first member, a first memory cell, and a controller. The first member includes first, second, and third regions. The first memory cell includes first and second magnetic layers, and a first nonmagnetic layer. The second magnetic layer is provided between the third region and the first magnetic layer. The first nonmagnetic layer is provided between the first and second magnetic layers. The controller is electrically connected to the first and second regions, and the first magnetic layer. The controller programs first information to the first memory cell by setting the first magnetic layer to a first electric potential. The controller programs second information to the first memory cell by setting the first magnetic layer to a second electric potential. The second electric potential is different from the first electric potential. The second information is different from the first information.

Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.

Abstract: A magnetic memory device includes a conductive member, a stacked body, and a controller. The stacked body includes a first magnetic layer, a second magnetic layer provided between the conductive member and the first magnetic layer, and a third magnetic layer stacked with the first magnetic layer and the second magnetic layer. The controller causes a current to flow in the conductive member. The controller causes a current to flow between the conductive member and the stacked body. The controller is able to identify three or more levels of an electrical resistance value of the stacked body.