Patents by Inventor Tomoaki Inokuchi
Tomoaki Inokuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10102894Abstract: A magnetic memory includes: a first and second terminals; a conductive layer including first to fourth regions, the first and fourth regions being electrically connected to the first and second terminals respectively; a first magnetoresistive element including: a first and second magnetic layers; a first nonmagnetic layer between the first and second magnetic layers; and a third terminal electrically connected to the first magnetic layer; a second magnetoresistive element including: a third and fourth magnetic layers; a second nonmagnetic layer between the third and fourth magnetic layers; and a fourth terminal electrically connected to the third magnetic layer; and a circuit configured to apply a write current between the first terminal and the second terminal and apply a first and second potentials to the third and fourth terminals respectively to write the first and second magnetoresistive elements, the first and second potentials being different from each other.Type: GrantFiled: September 7, 2017Date of Patent: October 16, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu Shimomura, Tomoaki Inokuchi, Hiroki Noguchi, Katsuhiko Koui, Yuuzo Kamiguchi, Kazutaka Ikegami, Hiroaki Yoda
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Publication number: 20180277746Abstract: A magnetic memory includes: first to fourth wirings; first and second terminals; a first conductive layer including first to third regions, the second region being between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; a first magnetoresistive element including a first and a second magnetic layer, and a first nonmagnetic layer disposed between the first and the magnetic layer; a first transistor including a third terminal electrically connected to the first magnetic layer, a fourth terminal electrically connected to the third wiring, and a first control terminal electrically connected to the first wiring; and a second transistor including a fifth terminal electrically connected to the first terminal, a sixth terminal electrically connected to the second wiring, and a second control terminal electrically connected to the first wiring.Type: ApplicationFiled: September 14, 2017Publication date: September 27, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiko ABE, Kazutaka IKEGAMI, Shinobu FUJITA, Katsuhiko KOUI, Tomoaki INOKUCHI, Satoshi SHIROTORI, Yuichi OHSAWA, Hideyuki SUGIYAMA, Hiroaki YODA, Naoharu SHIMOMURA, Yuuzo KAMIGUCHI
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Patent number: 10068946Abstract: A magnetic memory of an embodiment includes: a first nonmagnetic layer including a first and second faces; a first and second wirings disposed on a side of the first face; a third wiring disposed on a side of the second face; a first transistor, one of the source and the drain being connected to the first wiring, the other one being connected to the first nonmagnetic layer; a second transistor, one of source and drain being connected to the second wiring, the other one being connected to the first nonmagnetic layer; a magnetoresistive element disposed between the first nonmagnetic layer and the third wiring, a first terminal of the magnetoresistive element being connected to the first nonmagnetic layer; and a third transistor, one of source and drain of the third transistor being connected to the second terminal, the other one being connected to the third wiring.Type: GrantFiled: September 13, 2016Date of Patent: September 4, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu Shimomura, Hiroaki Yoda, Tadaomi Daibou, Yuuzo Kamiguchi, Yuichi Ohsawa, Tomoaki Inokuchi, Satoshi Shirotori
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Patent number: 10026465Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.Type: GrantFiled: March 8, 2017Date of Patent: July 17, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki Inokuchi, Naoharu Shimomura, Katsuhiko Koui, Yuuzo Kamiguchi, Satoshi Shirotori, Kazutaka Ikegami, Hiroaki Yoda
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Publication number: 20180159024Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.Type: ApplicationFiled: September 14, 2017Publication date: June 7, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Altansargai Buyandalai, Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi
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Publication number: 20180158499Abstract: A magnetic memory includes: a first and second terminals; a conductive layer including first to fourth regions, the first and fourth regions being electrically connected to the first and second terminals respectively; a first magnetoresistive element including: a first and second magnetic layers; a first nonmagnetic layer between the first and second magnetic layers; and a third terminal electrically connected to the first magnetic layer; a second magnetoresistive element including: a third and fourth magnetic layers; a second nonmagnetic layer between the third and fourth magnetic layers; and a fourth terminal electrically connected to the third magnetic layer; and a circuit configured to apply a write current between the first terminal and the second terminal and apply a first and second potentials to the third and fourth terminals respectively to write the first and second magnetoresistive elements, the first and second potentials being different from each other.Type: ApplicationFiled: September 7, 2017Publication date: June 7, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu SHIMOMURA, Tomoaki INOKUCHI, Hiroki NOGUCHI, Katsuhiko KOUI, Yuuzo KAMIGUCHI, Kazutaka IKEGAMI, Hiroaki YODA
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Patent number: 9985201Abstract: A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.Type: GrantFiled: March 7, 2017Date of Patent: May 29, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Shirotori, Hiroaki Yoda, Yuichi Ohsawa, Yuuzo Kamiguchi, Naoharu Shimomura, Tadaomi Daibou, Tomoaki Inokuchi
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Publication number: 20180114558Abstract: A magnetic memory according to an embodiment includes: a conductive layer including a first and second terminals; a plurality of magnetoresistive elements separately disposed on the conductive layer between the first and second terminals, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and a circuit configured to apply a first potential to the reference layers of the magnetoresistive elements and to flow a first write current between the first and second terminals, and configured to apply a second potential to the reference layer or the reference layers of one or more of the magnetoresistive elements to which data is to be written, and to flow a second write current between the first and second terminals in an opposite direction to the first write current.Type: ApplicationFiled: December 20, 2017Publication date: April 26, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Hiroaki Yoda, Naoharu Shimomura, Yuichi Ohsawa, Tadaomi Daibou, Tomoaki Inokuchi, Satoshi Shirotori, Altansargai Buyandalai, Yuuzo Kamiguchi
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Publication number: 20180090658Abstract: According to one embodiment, a thermoelectric conversion device includes a first stacked body comprising a plurality of first semiconductor layers of a first conductivity type, the first semiconductor layers spaced from each other in a first direction, a second stacked body comprising a plurality of second semiconductor layers of a second conductivity type, the second semiconductor layers spaced from each other in the first direction, and a first connection portion electrically connecting the first stacked body to the second stacked body, wherein the first stacked body has a plurality of first openings that extend inwardly of the first stacked body in the first direction, wherein a direction from the first stacked body to the second stacked body intersects the first direction, and wherein the second stacked body has a plurality of second openings extending inwardly of the second stacked body in the first direction.Type: ApplicationFiled: March 2, 2017Publication date: March 29, 2018Inventors: Yusuke KASAHARA, Miwa SATO, Yasuo AKATSUKA, Masamichi SUZUKI, Tomoaki INOKUCHI
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Patent number: 9916882Abstract: A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.Type: GrantFiled: September 12, 2016Date of Patent: March 13, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Shirotori, Hiroaki Yoda, Yuichi Ohsawa, Yuuzo Kamiguchi, Naoharu Shimomura, Tadaomi Daibou, Tomoaki Inokuchi
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Publication number: 20180040359Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.Type: ApplicationFiled: March 8, 2017Publication date: February 8, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki INOKUCHI, Naoharu SHIMOMURA, Katsuhiko KOUI, Yuuzo KAMIGUCHI, Satoshi SHIROTORI, Kazutaka IKEGAMI, Hiroaki YODA
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Patent number: 9881660Abstract: A magnetic memory according to an embodiment includes: a conductive layer including a first and second terminals; a plurality of magnetoresistive elements separately disposed on the conductive layer between the first and second terminals, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and a circuit configured to apply a first potential to the reference layers of the magnetoresistive elements and to flow a first write current between the first and second terminals, and configured to apply a second potential to the reference layer or the reference layers of one or more of the magnetoresistive elements to which data is to be written, and to flow a second write current between the first and second terminals in an opposite direction to the first write current.Type: GrantFiled: September 16, 2016Date of Patent: January 30, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroaki Yoda, Naoharu Shimomura, Yuichi Ohsawa, Tadaomi Daibou, Tomoaki Inokuchi, Satoshi Shirotori, Altansargai Buyandalai, Yuuzo Kamiguchi
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Patent number: 9842635Abstract: A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.Type: GrantFiled: March 8, 2016Date of Patent: December 12, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hideyuki Sugiyama, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
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Publication number: 20170271574Abstract: A magnetic memory according to an embodiment includes: a magnetoresistive device including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer between the first magnetic layer and the second magnetic layer; a first wiring electrically connected to the first magnetic layer; a second wiring that is electrically connected to the second magnetic layer and contains an antiferromagnetic material; a third wiring crossing the second wiring; an insulating layer between the second wiring and the third wiring; a first write circuit for applying a voltage between the second wiring and the third wiring; and a read circuit electrically connected to the first wiring and the second wiring.Type: ApplicationFiled: September 15, 2016Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki INOKUCHI, Mizue ISHIKAWA, Hideyuki SUGIYAMA, Yoshiaki SAITO
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Publication number: 20170179379Abstract: A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.Type: ApplicationFiled: March 7, 2017Publication date: June 22, 2017Applicant: Kabushiki Kaisha ToshibaInventors: SATOSHI SHIROTORI, Hiroaki Yoda, Yuichi Ohsawa, Yuuzo Kamiguchi, Naoharu Shimomura, Tadaomi Daibou, Tomoaki Inokuchi
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Publication number: 20170169872Abstract: A magnetic memory according to an embodiment includes: a conductive layer including a first and second terminals; a plurality of magnetoresistive elements separately disposed on the conductive layer between the first and second terminals, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and a circuit configured to apply a first potential to the reference layers of the magnetoresistive elements and to flow a first write current between the first and second terminals, and configured to apply a second potential to the reference layer or the reference layers of one or more of the magnetoresistive elements to which data is to be written, and to flow a second write current between the first and second terminals in an opposite direction to the first write current.Type: ApplicationFiled: September 16, 2016Publication date: June 15, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroaki YODA, Naoharu SHIMOMURA, Yuichi OHSAWA, Tadaomi DAIBOU, Tomoaki INOKUCHI, Satoshi SHIROTORI, Altansargai BUYANDALAI, Yuuzo KAMIGUCHI
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Publication number: 20170141158Abstract: A magnetic memory according to an embodiment includes: a conductive nonmagnetic layer including a first terminal, a second terminal, and a region between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer disposed between the region and the first magnetic layer; and a nonmagnetic intermediate layer disposed between the first magnetic layer and the second magnetic layer; a transistor including a third terminal, a fourth terminal, and a control terminal, the third terminal being electrically connected to the first terminal; a first wiring electrically connected to the first magnetic layer and the fourth terminal; a second wiring electrically connected to the control terminal; and a third wiring electrically connected to the second terminal.Type: ApplicationFiled: January 31, 2017Publication date: May 18, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tadaomi DAIBOU, Naoharu SHIMOMURA, Yuuzo KAMIGUCHI, Hiroaki YODA, Yuichi OHSAWA, Tomoaki INOKUCHI, Satoshi SHIROTORI
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Publication number: 20170076769Abstract: A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.Type: ApplicationFiled: September 12, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Satoshi SHIROTORI, Hiroaki YODA, Yuichi OHSAWA, Yuuzo KAMIGUCHI, Naoharu SHIMOMURA, Tadaomi DAIBOU, Tomoaki INOKUCHI
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Publication number: 20170076770Abstract: A magnetic memory according to an embodiment includes: a conductive nonmagnetic layer including a first terminal, a second terminal, and a region between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer disposed between the region and the first magnetic layer; and a nonmagnetic intermediate layer disposed between the first magnetic layer and the second magnetic layer; a transistor including a third terminal, a fourth terminal, and a control terminal, the third terminal being electrically connected to the first terminal; a first wiring electrically connected to the first magnetic layer and the fourth terminal; a second wiring electrically connected to the control terminal; and a third wiring electrically connected to the second terminal.Type: ApplicationFiled: September 13, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tadaomi DAIBOU, Naoharu SHIMOMURA, Yuuzo KAMIGUCHI, Hiroaki YODA, Yuichi OHSAWA, Tomoaki INOKUCHI, Satoshi SHIROTORI
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Publication number: 20170077177Abstract: A magnetic memory of an embodiment includes: a first nonmagnetic layer including a first and second faces; a first and second wirings disposed on a side of the first face; a third wiring disposed on a side of the second face; a first transistor, one of the source and the drain being connected to the first wiring, the other one being connected to the first nonmagnetic layer; a second transistor, one of source and drain being connected to the second wiring, the other one being connected to the first nonmagnetic layer; a magnetoresistive element disposed between the first nonmagnetic layer and the third wiring, a first terminal of the magnetoresistive element being connected to the first nonmagnetic layer; and a third transistor, one of source and drain of the third transistor being connected to the second terminal, the other one being connected to the third wiring.Type: ApplicationFiled: September 13, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Naoharu SHIMOMURA, Hiroaki YODA, Tadaomi DAIBOU, Yuuzo KAMIGUCHI, Yuichi OHSAWA, Tomoaki INOKUCHI, Satoshi SHIROTORI