Abstract: A program processing device comprises a CPU for carrying out predetermined processing according to a program; an internal memory storing the program and data generated by the CPU by carrying out the program, and a data acquiring circuit connected to an external program processing device, for acquiring the program from the external program processing device to write into the internal memory, wherein the CPU, the internal memory, a debug processing circuit, and the data acquiring circuit are integrally mounted on the same semiconductor substrate.

Abstract: A data recording device for recording data on an optical disc by irradiating a laser pulse on the optical disc while controlling rotation of the optical disc at a constant angular velocity. The device includes a laser condition varying unit that changes a peak value of the laser pulse in accordance with a value relating to a linear velocity of the optical disc at a position at which the laser pulse is irradiated.

Abstract: A method and device for generating a clock signal accurately synchronized with a wobble signal including jitter even if there are manufacturing differences between voltage controlled oscillators. The clock signal generation device includes a voltage controlled oscillator for generating a clock signal corresponding to each of a plurality of oscillation characteristics. The clock signal generation device applies a test voltage to a voltage controlled oscillator with a voltage control device and sequentially identifies a plurality of oscillation characteristics set for the voltage controlled oscillator. The clock signal generation device selects one of the identified oscillation characteristics that has a frequency range with a generally middle part in which the frequency of a wobble signal is located and has a smaller gain.

Abstract: A CD-ROM decoder for processing digital data while buffering the digital data in a buffer RAM. The CD-ROM decoder includes a host interface for storing the digital data in the buffer RAM. An EDC processing circuit generates an error detection code using the digital data read from the buffer RAM in a block unit. An ECC processing circuit generates an error correction code with the digital data and the error detection code. An internal RAM stores the digital data and adds the error detection code and the error correction code to the digital data when storing the digital data. A digital signal processor outputs the digital data, the error detection code, and the error correction code that are stored in the internal RAM in a block unit.

Abstract: A data processor that reduces the chip area of a semiconductor substrate. The data processor includes a detection circuit for generating an error detection code with digital data. A correction circuit generates an error correction code with the digital data that includes the error detection code. A control circuit controls the detection processing circuit and the correction processing circuit in accordance with a control program. The data processor further includes a first external memory and a serial/parallel conversion circuit. The first external memory stores a control program. The serial/parallel conversion circuit receives data of the control program in a serial state from the first external memory and provides a second external memory with the control program data in a parallel state when the data processor is activated.

Abstract: A data processor that reduces the chip area of a semiconductor substrate. The data processor includes a detection circuit for generating an error detection code with digital data. A correction circuit generates an error correction code with the digital data that includes the error detection code. A control circuit controls the detection processing circuit and the correction processing circuit in accordance with a control program. The data processor further includes a first external memory and a serial/parallel conversion circuit. The first external memory stores a control program. The serial/parallel conversion circuit receives data of the control program in a serial state from the first external memory and provides a second external memory with the control program data in a parallel state when the data processor is activated.

Abstract: A method and device for generating a clock signal accurately synchronized with a wobble signal including jitter even if there are manufacturing differences between voltage controlled oscillators. The clock signal generation device includes a voltage controlled oscillator for generating a clock signal corresponding to each of a plurality of oscillation characteristics. The clock signal generation device applies a test voltage to a voltage controlled oscillator with a voltage control device and sequentially identifies a plurality of oscillation characteristics set for the voltage controlled oscillator. The clock signal generation device selects one of the identified oscillation characteristics that has a frequency range with a generally middle part in which the frequency of a wobble signal is located and has a smaller gain.

Abstract: A packaged semiconductor device that enables testing of semiconductor chips incorporated therein in a simplified and efficient manner. The semiconductor device includes a packaged logic chip for processing data and a packaged memory chip for storing data that is processed by or that is to be processed by the logic circuit. The semiconductor device has an automatic rewrite circuit and a selector. The automatic rewrite circuit automatically writes test data to the memory circuit in accordance with a command signal from a tester. The selector selectively switches between accessing of the memory circuit by the automatic rewrite circuit and accessing of the memory circuit by the logic circuit. The tester provides the automatic rewrite circuit with a test start command signal to start testing the logic circuit.

Abstract: A data processor that reduces the chip area of a semiconductor substrate. The data processor includes a detection circuit for generating an error detection code with digital data. A correction circuit generates an error correction code with the digital data that includes the error detection code. A control circuit controls the detection processing circuit and the correction processing circuit in accordance with a control program. The data processor further includes a first external memory and a serial/parallel conversion circuit. The first external memory stores a control program. The serial/parallel conversion circuit receives data of the control program in a serial state from the first external memory and provides a second external memory with the control program data in a parallel state when the data processor is activated.

Abstract: A CD-ROM decoder for processing digital data while buffering the digital data in a buffer RAM. The CD-ROM decoder includes a host interface for storing the digital data in the buffer RAM. An EDC processing circuit generates an error detection code using the digital data read from the buffer RAM in a block unit. An ECC processing circuit generates an error correction code with the digital data and the error detection code. An internal RAM stores the digital data and adds the error detection code and the error correction code to the digital data when storing the digital data. A digital signal processor outputs the digital data, the error detection code, and the error correction code that are stored in the internal RAM in a block unit.

Abstract: A data recording device for recording data on an optical disc by irradiating a laser pulse on the optical disc while controlling rotation of the optical disc at a constant angular velocity. The device includes a laser condition varying unit that changes a peak value of the laser pulse in accordance with a value relating to a linear velocity of the optical disc at a position at which the laser pulse is irradiated.

Abstract: The bonding material for an electronic component comprises a metal material and fine resin particles dispersed in the metal material. Such a material may form an electrical “bump” for the component.

Abstract: A data reproduction apparatus is provided to supply audio data without sound skipping caused by positional deviation in read position, while avoiding an increase in circuit area. In one embodiment, the data reproduction apparatus includes a reading unit for optically reading data recorded on a recording medium. A first signal processing circuit produces a format data signal based on the data read by the reading unit. A second signal processing circuit performs a demodulation process on the format data signal to produce a demodulated format data signal including main data and subcode data. The second signal processing circuit also subjects the main data signal to a decoding process to produce a reproduced data signal. A buffer memory temporally stores the reproduced data signal. A shockproof controller controls the writing and reading of the reproduced data signal into and from the buffer memory.

Abstract: A CD-ROM decoder comprising a DSP interface, an error correcting portion or a RAM access portion, a host interface, and a subcode reading portion. A control microcomputer and a buffer RAM are connected to the CD-ROM decoder. The DSP interface subjects CD-ROM data to a descrambling processing and writes it into the buffer RAM. After code errors of the CD-ROM data written into the buffer RAM are corrected, the CD-ROM data is output from the host interface to a host computer. The subcode reading portion reads subcode data for 98 frames and writes it into the buffer RAM. The subcode data is output from the host interface to the host computer. The subcode data is transferred not through the control microcomputer but directly to the host computer. Alternatively, the RAM access portion reads selected CD-ROM data from the host interface into the buffer RAM. As a result, the load applied to the control microcomputer for controlling the operation of the CD-ROM decoder is reduced.